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src/cpu/amd/model_fxx/powernow_api.c Fix checkpatch errors + warnings 

Fix line over 80 characters, spaces required around comparisons,space
required after close brace '}', comma ',', semicolon ';',  space
prohibited after ')' errors and warnings

Change-Id: I5585f55a606d4f2149b17ac92cbdd832f242630e
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/20099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Evelyn Huang 2017-06-07 15:18:26 -06:00 committed by Martin Roth
parent 82651463e3
commit f6934f5c6c
1 changed files with 219 additions and 162 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

155
src/cpu/amd/model_fxx/powernow_acpi.c
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@ -26,9 +26,11 @@
#include <cpu/amd/amdk8_sysconf.h> #include <cpu/amd/amdk8_sysconf.h>
#include <arch/cpu.h> #include <arch/cpu.h>
static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid, static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq,
u8 *pstate_fid, u32 *pstate_power, int coreID, u8 *pstate_vid, u8 *pstate_fid,
u32 pcontrol_blk, u8 plen, u8 onlyBSP, u32 control) u32 *pstate_power, int coreID,
u32 pcontrol_blk, u8 plen, u8 onlyBSP,
u32 control)
{ {
int i; int i;
@ -134,7 +136,9 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
{0x12, 0x1, 0x4, 20} {0x12, 0x1, 0x4, 20}
}; };
/* Get the Processor Brand String using cpuid(0x8000000x) command x=2,3,4 */ /* Get the Processor Brand String using
* cpuid(0x8000000x) command x=2,3,4
*/
cpuid1 = cpuid(0x80000002); cpuid1 = cpuid(0x80000002);
v = (u32 *) processor_brand; v = (u32 *) processor_brand;
v[0] = cpuid1.eax; v[0] = cpuid1.eax;
@ -155,7 +159,8 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
printk(BIOS_INFO, "processor_brand=%s\n", processor_brand); printk(BIOS_INFO, "processor_brand=%s\n", processor_brand);
/* /*
* Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit. * Based on the CPU socket type,cmp_cap and pwr_lmt,
* get the power limit.
* socket_type : 0x10 SocketF; 0x11 AM2/ASB1; 0x12 S1G1 * socket_type : 0x10 SocketF; 0x11 AM2/ASB1; 0x12 S1G1
* cmp_cap : 0x0 SingleCore; 0x1 DualCore * cmp_cap : 0x0 SingleCore; 0x1 DualCore
*/ */
@ -217,14 +222,16 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
/* /*
* Formula1: CPUFreq = FID * fid_multiplier + 800 * Formula1: CPUFreq = FID * fid_multiplier + 800
* Formula2: CPUVolt = 1550 - VID * 25 (mv) * Formula2: CPUVolt = 1550 - VID * 25 (mv)
* Formula3: Power = (PwrLmt * P[N]Frequency*(P[N]Voltage^2))/(P[0]Frequency * P[0]Voltage^2)) * Formula3: Power = (PwrLmt * P[N]Frequency*(P[N]Voltage^2))
/(P[0]Frequency * P[0]Voltage^2))
*/ */
/* Construct P0(P[Max]) state */ /* Construct P0(P[Max]) state */
Max_feq = Max_fid * fid_multiplier + 800; Max_feq = Max_fid * fid_multiplier + 800;
if (Max_fid == 0x2A && Max_vid != 0x0) { if (Max_fid == 0x2A && Max_vid != 0x0) {
Min_fid = 0x2; Min_fid = 0x2;
Pstate_fid[0] = Start_fid + 0xA; /* Start Frequency + 1GHz */ /* Start Frequency + 1GHz */
Pstate_fid[0] = Start_fid + 0xA;
Pstate_feq[0] = Pstate_fid[0] * fid_multiplier + 800; Pstate_feq[0] = Pstate_fid[0] * fid_multiplier + 800;
Min_vid = Start_vid; Min_vid = Start_vid;
Pstate_vid[0] = Max_vid + 0x2; /* Maximum Voltage - 50mV */ Pstate_vid[0] = Max_vid + 0x2; /* Maximum Voltage - 50mV */
@ -250,50 +257,67 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
Cur_feq = Max_feq; Cur_feq = Max_feq;
Cur_fid = Max_fid; Cur_fid = Max_fid;
/* Construct P1 state */ /* Construct P1 state */
if (((Max_fid & 0x1) != 0) && ((Max_fid - 0x1) >= (Min_fid + 0x8))) { /* odd value */ /* if odd value */
if (((Max_fid & 0x1) != 0) && ((Max_fid - 0x1) >= (Min_fid + 0x8))) {
Pstate_fid[1] = Max_fid - 0x1; Pstate_fid[1] = Max_fid - 0x1;
Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800; Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800;
Cur_fid = Pstate_fid[1]; Cur_fid = Pstate_fid[1];
Cur_feq = Pstate_feq[1]; Cur_feq = Pstate_feq[1];
if (((Pstate_vid[0] & 0x1) != 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* odd value */ /* if odd value */
if (((Pstate_vid[0] & 0x1) != 0) &&
((Pstate_vid[0] - 0x1) < Min_vid)) {
Pstate_vid[1] = Pstate_vid[0] + 0x1; Pstate_vid[1] = Pstate_vid[0] + 0x1;
Pstate_volt[1] = 1550 - Pstate_vid[1] * 25; Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
Pstate_power[1] = Pstate_power[1] =
((unsigned long long)Pstate_power[0] * ((unsigned long long)Pstate_power[0] *
Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1]) / Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1]) /
((unsigned long long)Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]); ((unsigned long long)Pstate_feq[0] *
Pstate_volt[0] *
Pstate_volt[0]);
} }
if (((Pstate_vid[0] & 0x1) == 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* even value */ /* if even value */
if (((Pstate_vid[0] & 0x1) == 0) &&
((Pstate_vid[0] - 0x1) < Min_vid)) {
Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef; Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef;
Pstate_volt[1] = 1550 - Pstate_vid[1] * 25; Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
Pstate_power[1] = Pstate_power[1] =
((unsigned long long)Pstate_power[0] * ((unsigned long long)Pstate_power[0] *
Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1]) / Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1]) /
((unsigned long long)Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]); ((unsigned long long)Pstate_feq[0] *
Pstate_volt[0] *
Pstate_volt[0]);
} }
Pstate_num++; Pstate_num++;
} }
/* if even value */
if (((Max_fid & 0x1) == 0) && ((Max_fid - 0x2) >= (Min_fid + 0x8))) { /* even value */ if (((Max_fid & 0x1) == 0) && ((Max_fid - 0x2) >= (Min_fid + 0x8))) {
Pstate_fid[1] = Max_fid - 0x2; Pstate_fid[1] = Max_fid - 0x2;
Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800; Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800;
Cur_fid = Pstate_fid[1]; Cur_fid = Pstate_fid[1];
Cur_feq = Pstate_feq[1]; Cur_feq = Pstate_feq[1];
if (((Pstate_vid[0] & 0x1) != 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* odd value */ /* if odd value */
if (((Pstate_vid[0] & 0x1) != 0) &&
((Pstate_vid[0] - 0x1) < Min_vid)) {
Pstate_vid[1] = Pstate_vid[0] + 0x1; Pstate_vid[1] = Pstate_vid[0] + 0x1;
Pstate_volt[1] = 1550 - Pstate_vid[1] * 25; Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
Pstate_power[1] = Pstate_power[1] =
((unsigned long long)Pstate_power[0] * ((unsigned long long)Pstate_power[0] *
Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1]) / Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1]) /
((unsigned long long)Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]); ((unsigned long long)Pstate_feq[0] *
Pstate_volt[0] *
Pstate_volt[0]);
} }
if (((Pstate_vid[0] & 0x1) == 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* even value */ /* if even value */
if (((Pstate_vid[0] & 0x1) == 0) &&
((Pstate_vid[0] - 0x1) < Min_vid)) {
Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef; Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef;
Pstate_volt[1] = 1550 - Pstate_vid[1] * 25; Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
Pstate_power[1] = Pstate_power[1] =
((unsigned long long)Pstate_power[0] * ((unsigned long long)Pstate_power[0] *
Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1]) / Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1]) /
((unsigned long long)Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]); ((unsigned long long)Pstate_feq[0] *
Pstate_volt[0] *
Pstate_volt[0]);
} }
Pstate_num++; Pstate_num++;
@ -319,8 +343,10 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
1550 - Pstate_vid[Pstate_num] * 25; 1550 - Pstate_vid[Pstate_num] * 25;
Pstate_power[Pstate_num] = Pstate_power[Pstate_num] =
((unsigned long long)Pstate_power[0] * ((unsigned long long)Pstate_power[0] *
Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] * Pstate_volt[Pstate_num]) / Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
((unsigned long long)Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]); Pstate_volt[Pstate_num]) /
((unsigned long long)Pstate_feq[0] *
Pstate_volt[0] * Pstate_volt[0]);
} }
Pstate_num++; Pstate_num++;
} }
@ -335,8 +361,10 @@ nointpstatesup:
Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25; Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25;
Pstate_power[Pstate_num] = Pstate_power[Pstate_num] =
((unsigned long long)Pstate_power[0] * ((unsigned long long)Pstate_power[0] *
Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] * Pstate_volt[Pstate_num]) / Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
((unsigned long long)Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]); Pstate_volt[Pstate_num]) /
((unsigned long long)Pstate_feq[0] * Pstate_volt[0] *
Pstate_volt[0]);
Pstate_num++; Pstate_num++;
} else { } else {
Pstate_fid[Pstate_num] = Start_fid; Pstate_fid[Pstate_num] = Start_fid;
@ -346,8 +374,10 @@ nointpstatesup:
Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25; Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25;
Pstate_power[Pstate_num] = Pstate_power[Pstate_num] =
((unsigned long long)Pstate_power[0] * ((unsigned long long)Pstate_power[0] *
Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] * Pstate_volt[Pstate_num]) / Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
((unsigned long long)Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]); Pstate_volt[Pstate_num]) /
((unsigned long long)Pstate_feq[0] * Pstate_volt[0] *
Pstate_volt[0]);
Pstate_num++; Pstate_num++;
} }
@ -356,7 +386,8 @@ nointpstatesup:
for (index = 0; index < Pstate_num; index++) { for (index = 0; index < Pstate_num; index++) {
printk(BIOS_INFO, "Pstate_freq[%d] = %dMHz\t", index, printk(BIOS_INFO, "Pstate_freq[%d] = %dMHz\t", index,
Pstate_feq[index]); Pstate_feq[index]);
printk(BIOS_INFO, "Pstate_vid[%d] = %d\t", index, Pstate_vid[index]); printk(BIOS_INFO, "Pstate_vid[%d] = %d\t",
index, Pstate_vid[index]);
printk(BIOS_INFO, "Pstate_volt[%d] = %dmv\t", index, printk(BIOS_INFO, "Pstate_volt[%d] = %dmv\t", index,
Pstate_volt[index]); Pstate_volt[index]);
printk(BIOS_INFO, "Pstate_power[%d] = %dmw\n", index, printk(BIOS_INFO, "Pstate_power[%d] = %dmw\n", index,
@ -412,13 +443,21 @@ struct pstate {
}; };
struct cpuentry { struct cpuentry {
uint16_t modelnr; /* numeric model value, unused in code */ /* numeric model value, unused in code */
uint8_t brandID; /* CPUID 8000_0001h EBX [11:6] (BrandID) */ uint16_t modelnr;
uint32_t cpuid; /* CPUID 8000_0001h EAX [31:0] (CPUID) */ /* CPUID 8000_0001h EBX [11:6] (BrandID) */
uint8_t maxFID; /* FID/VID Status MaxFID Field */ uint8_t brandID;
uint8_t startFID; /* FID/VID Status StartFID Field */ /* CPUID 8000_0001h EAX [31:0] (CPUID) */
uint16_t pwr:12; /* Thermal Design Power of Max P-State *10 (fixed point) */ uint32_t cpuid;
/* Other MAX P state are read from CPU, other P states in following table */ /* FID/VID Status MaxFID Field */
uint8_t maxFID;
/* FID/VID Status StartFID Field */
uint8_t startFID;
/* Thermal Design Power of Max P-State *10 (fixed point) */
uint16_t pwr:12;
/* Other MAX P state are read from CPU,
* other P states in following table
*/
struct pstate pstates[MAXP]; struct pstate pstates[MAXP];
}; };
@ -602,7 +641,8 @@ struct cpuentry entr[] = {
{{1800, 1400, 660}, {1000, 1100, 220} } }, {{1800, 1400, 660}, {1000, 1100, 220} } },
/* ADA3700AEP5AR */ /* ADA3700AEP5AR */
{3700, 0x4, 0xf4a, 0x10, 0x10, 890, {3700, 0x4, 0xf4a, 0x10, 0x10, 890,
{{2200, 1400, 720}, {2000, 1300, 530}, {1800, 1200, 390}, {1000, 1100, 220}}}, {{2200, 1400, 720}, {2000, 1300, 530},
{1800, 1200, 390}, {1000, 1100, 220} } },
/* ADA2800AEP4AX */ /* ADA2800AEP4AX */
{2800, 0x4, 0xfc0, 0xa, 0xa, 890, {2800, 0x4, 0xfc0, 0xa, 0xa, 890,
{{1000, 1100, 220} } }, {{1000, 1100, 220} } },
@ -614,7 +654,8 @@ struct cpuentry entr[] = {
{{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220} } }, {{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220} } },
/* ADA3400AEP4AX */ /* ADA3400AEP4AX */
{3400, 0x4, 0xfc0, 0x10, 0x10, 890, {3400, 0x4, 0xfc0, 0x10, 0x10, 890,
{{2200, 1400, 720}, {2000, 1300, 530}, {1800, 1200, 390}, {1000, 1100, 220}}}, {{2200, 1400, 720}, {2000, 1300, 530},
{1800, 1200, 390}, {1000, 1100, 220} } },
/* ADA3500DEP4AS */ /* ADA3500DEP4AS */
{3500, 0x4, 0xf7a, 0xe, 0xe, 890, {3500, 0x4, 0xf7a, 0xe, 0xe, 890,
{{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220} } }, {{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220} } },
@ -623,10 +664,12 @@ struct cpuentry entr[] = {
{{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220} } }, {{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220} } },
/* ADA3800DEP4AW */ /* ADA3800DEP4AW */
{3800, 0x4, 0xff0, 0x10, 0x10, 890, {3800, 0x4, 0xff0, 0x10, 0x10, 890,
{{2200, 1400, 720}, {2000, 1300, 530}, {1800, 1200, 390}, {1000, 1100, 220}}}, {{2200, 1400, 720}, {2000, 1300, 530},
{1800, 1200, 390}, {1000, 1100, 220} } },
/* ADA4000DEP5AS */ /* ADA4000DEP5AS */
{4000, 0x4, 0xf7a, 0x10, 0x10, 890, {4000, 0x4, 0xf7a, 0x10, 0x10, 890,
{{2200, 1400, 720}, {2000, 1300, 530}, {1800, 1200, 390}, {1000, 1100, 220}}}, {{2200, 1400, 720}, {2000, 1300, 530},
{1800, 1200, 390}, {1000, 1100, 220} } },
/* ADA3500DAA4BN */ /* ADA3500DAA4BN */
{3500, 0x4, 0x20f71, 0xe, 0xe, 670, {3500, 0x4, 0x20f71, 0xe, 0xe, 670,
{{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275} } }, {{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275} } },
@ -635,16 +678,19 @@ struct cpuentry entr[] = {
{{2000, 1350, 830}, {1800, 1300, 704}, {1000, 1100, 361} } }, {{2000, 1350, 830}, {1800, 1300, 704}, {1000, 1100, 361} } },
/* ADA4000DAA5BN */ /* ADA4000DAA5BN */
{4000, 0x4, 0x20f71, 0x10, 0x10, 853, {4000, 0x4, 0x20f71, 0x10, 0x10, 853,
{{2200, 1350, 830}, {2000, 1300, 706}, {1800, 1250, 596}, {1000, 1100, 350}}}, {{2200, 1350, 830}, {2000, 1300, 706},
{1800, 1250, 596}, {1000, 1100, 350} } },
/* ADA3700DKA5CF */ /* ADA3700DKA5CF */
{3700, 0x4, 0x30f72, 0xe, 0xe, 853, {3700, 0x4, 0x30f72, 0xe, 0xe, 853,
{{2000, 1350, 830}, {1800, 1300, 704}, {1000, 1100, 361} } }, {{2000, 1350, 830}, {1800, 1300, 704}, {1000, 1100, 361} } },
/* ADA4000DKA5CF */ /* ADA4000DKA5CF */
{4000, 0x4, 0x30f72, 0x10, 0x10, 853, {4000, 0x4, 0x30f72, 0x10, 0x10, 853,
{{2200, 1350, 830}, {2000, 1300, 706}, {1800, 1250, 596}, {1000, 1100, 350}}}, {{2200, 1350, 830}, {2000, 1300, 706},
{1800, 1250, 596}, {1000, 1100, 350} } },
/* ADA3800DAA4BP */ /* ADA3800DAA4BP */
{3800, 0x4, 0x20ff0, 0x10, 0x10, 853, {3800, 0x4, 0x20ff0, 0x10, 0x10, 853,
{{2200, 1350, 830}, {2000, 1300, 706}, {1800, 1250, 596}, {1000, 1100, 350}}}, {{2200, 1350, 830}, {2000, 1300, 706},
{1800, 1250, 596}, {1000, 1100, 350} } },
/* ADA3000DIK4BI */ /* ADA3000DIK4BI */
{3000, 0x4, 0x10ff0, 0xa, 0xa, 670, {3000, 0x4, 0x10ff0, 0xa, 0xa, 670,
{{1000, 1100, 210} } }, {{1000, 1100, 210} } },
@ -677,7 +723,8 @@ struct cpuentry entr[] = {
{{1800, 1350, 647}, {1000, 1100, 286} } }, {{1800, 1350, 647}, {1000, 1100, 286} } },
/* ADA3800DAA4BW */ /* ADA3800DAA4BW */
{3800, 0x4, 0x20ff2, 0x10, 0x10, 853, {3800, 0x4, 0x20ff2, 0x10, 0x10, 853,
{{2200, 1350, 830}, {2000, 1300, 706}, {1800, 1250, 596}, {1000, 1100, 350}}}, {{2200, 1350, 830}, {2000, 1300, 706},
{1800, 1250, 596}, {1000, 1100, 350} } },
/* ADA3000AIK4BX */ /* ADA3000AIK4BX */
{3000, 0x4, 0x20fc2, 0xc, 0xc, 510, {3000, 0x4, 0x20fc2, 0xc, 0xc, 510,
{{1800, 1350, 428}, {1000, 1100, 189} } }, {{1800, 1350, 428}, {1000, 1100, 189} } },
@ -746,7 +793,8 @@ struct cpuentry entr[] = {
{{2000, 1300, 1056}, {1800, 1250, 891}, {1000, 1100, 490} } }, {{2000, 1300, 1056}, {1800, 1250, 891}, {1000, 1100, 490} } },
/* ADA4800DAA6CD */ /* ADA4800DAA6CD */
{4800, 0x5, 0x20f32, 0x10, 0x10, 1100, {4800, 0x5, 0x20f32, 0x10, 0x10, 1100,
{{2200, 1300, 1056}, {2000, 1250, 891}, {1800, 1200, 748}, {1000, 1100, 466}}}, {{2200, 1300, 1056}, {2000, 1250, 891},
{1800, 1200, 748}, {1000, 1100, 466} } },
/* ADA3800DAA5BV */ /* ADA3800DAA5BV */
{3800, 0x5, 0x20fb1, 0xc, 0xc, 890, {3800, 0x5, 0x20fb1, 0xc, 0xc, 890,
{{1800, 1300, 846}, {1000, 1100, 401} } }, {{1800, 1300, 846}, {1000, 1100, 401} } },
@ -755,7 +803,8 @@ struct cpuentry entr[] = {
{{2000, 1300, 846}, {1800, 1250, 709}, {1000, 1100, 376} } }, {{2000, 1300, 846}, {1800, 1250, 709}, {1000, 1100, 376} } },
/* ADA4600DAA5BV */ /* ADA4600DAA5BV */
{4600, 0x5, 0x20fb1, 0x10, 0x10, 1100, {4600, 0x5, 0x20fb1, 0x10, 0x10, 1100,
{{2200, 1300, 1056}, {2000, 1250, 891}, {1800, 1200, 748}, {1000, 1100, 466}}}, {{2200, 1300, 1056}, {2000, 1250, 891},
{1800, 1200, 748}, {1000, 1100, 466} } },
}; };
static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
@ -846,16 +895,23 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
Pstate_power[0] = data->pwr * 100; Pstate_power[0] = data->pwr * 100;
for (Pstate_num = 1; for (Pstate_num = 1;
(Pstate_num <= MAXP) && (data->pstates[Pstate_num - 1].freqMhz != 0); (Pstate_num <= MAXP) &&
(data->pstates[Pstate_num - 1].freqMhz != 0);
Pstate_num++) { Pstate_num++) {
Pstate_fid[Pstate_num] = freq_to_fid(data->pstates[Pstate_num - 1].freqMhz) & 0x3f; Pstate_fid[Pstate_num] =
Pstate_feq[Pstate_num] = data->pstates[Pstate_num - 1].freqMhz; freq_to_fid(data->pstates[Pstate_num - 1].freqMhz) & 0x3f;
Pstate_vid[Pstate_num] = vid_to_reg(data->pstates[Pstate_num - 1].voltage); Pstate_feq[Pstate_num] =
Pstate_power[Pstate_num] = data->pstates[Pstate_num - 1].tdp * 100; data->pstates[Pstate_num - 1].freqMhz;
Pstate_vid[Pstate_num] =
vid_to_reg(data->pstates[Pstate_num - 1].voltage);
Pstate_power[Pstate_num] =
data->pstates[Pstate_num - 1].tdp * 100;
} }
for (i = 0; i < Pstate_num; i++) for (i = 0; i < Pstate_num; i++)
printk(BIOS_DEBUG, "P#%d freq %d [MHz] voltage %d [mV] TDP %d [mW]\n", i, printk(BIOS_DEBUG,
"P#%d freq %d [MHz] voltage %d [mV] TDP %d [mW]\n",
i,
Pstate_feq[i], Pstate_feq[i],
vid_from_reg(Pstate_vid[i]), vid_from_reg(Pstate_vid[i]),
Pstate_power[i]); Pstate_power[i]);
@ -866,7 +922,8 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
continue; continue;
for (i = 0; i < (cmp_cap + 1); i++) { for (i = 0; i < (cmp_cap + 1); i++) {
write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid, write_pstates_for_core(Pstate_num,
Pstate_feq, Pstate_vid,
Pstate_fid, Pstate_power, index+i, Pstate_fid, Pstate_power, index+i,
pcontrol_blk, plen, onlyBSP, control); pcontrol_blk, plen, onlyBSP, control);
} }