src/cpu/amd/model_fxx/powernow_api.c Fix checkpatch errors + warnings
Fix line over 80 characters, spaces required around comparisons,space required after close brace '}', comma ',', semicolon ';', space prohibited after ')' errors and warnings Change-Id: I5585f55a606d4f2149b17ac92cbdd832f242630e Signed-off-by: Evelyn Huang <evhuang@google.com> Reviewed-on: https://review.coreboot.org/20099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Evelyn Huang
Martin Roth
parent
82651463e3
commit
f6934f5c6c
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@ -26,15 +26,17 @@
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#include <cpu/amd/amdk8_sysconf.h>
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#include <arch/cpu.h>
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static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid,
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u8 *pstate_fid, u32 *pstate_power, int coreID,
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u32 pcontrol_blk, u8 plen, u8 onlyBSP, u32 control)
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static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq,
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u8 *pstate_vid, u8 *pstate_fid,
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u32 *pstate_power, int coreID,
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u32 pcontrol_blk, u8 plen, u8 onlyBSP,
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u32 control)
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{
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int i;
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if ((onlyBSP) && (coreID != 0)) {
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plen = 0;
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pcontrol_blk = 0;
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plen = 0;
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pcontrol_blk = 0;
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}
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acpigen_write_processor(coreID, pcontrol_blk, plen);
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@ -44,7 +46,7 @@ static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vi
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/* add later to total sum */
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acpigen_write_package(pstate_num);
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for (i = 0;i < pstate_num;i++) {
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for (i = 0; i < pstate_num; i++) {
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u32 status, c2;
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c2 = control | (pstate_vid[i] << 6) |
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pstate_fid[i];
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@ -134,7 +136,9 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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{0x12, 0x1, 0x4, 20}
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};
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/* Get the Processor Brand String using cpuid(0x8000000x) command x=2,3,4 */
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/* Get the Processor Brand String using
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* cpuid(0x8000000x) command x=2,3,4
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*/
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cpuid1 = cpuid(0x80000002);
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v = (u32 *) processor_brand;
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v[0] = cpuid1.eax;
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@ -155,7 +159,8 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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printk(BIOS_INFO, "processor_brand=%s\n", processor_brand);
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/*
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* Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
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* Based on the CPU socket type,cmp_cap and pwr_lmt,
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* get the power limit.
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* socket_type : 0x10 SocketF; 0x11 AM2/ASB1; 0x12 S1G1
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* cmp_cap : 0x0 SingleCore; 0x1 DualCore
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*/
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@ -217,14 +222,16 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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/*
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* Formula1: CPUFreq = FID * fid_multiplier + 800
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* Formula2: CPUVolt = 1550 - VID * 25 (mv)
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* Formula3: Power = (PwrLmt * P[N]Frequency*(P[N]Voltage^2))/(P[0]Frequency * P[0]Voltage^2))
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* Formula3: Power = (PwrLmt * P[N]Frequency*(P[N]Voltage^2))
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/(P[0]Frequency * P[0]Voltage^2))
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*/
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/* Construct P0(P[Max]) state */
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Max_feq = Max_fid * fid_multiplier + 800;
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if (Max_fid == 0x2A && Max_vid != 0x0) {
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Min_fid = 0x2;
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Pstate_fid[0] = Start_fid + 0xA; /* Start Frequency + 1GHz */
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/* Start Frequency + 1GHz */
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Pstate_fid[0] = Start_fid + 0xA;
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Pstate_feq[0] = Pstate_fid[0] * fid_multiplier + 800;
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Min_vid = Start_vid;
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Pstate_vid[0] = Max_vid + 0x2; /* Maximum Voltage - 50mV */
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@ -250,50 +257,67 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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Cur_feq = Max_feq;
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Cur_fid = Max_fid;
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/* Construct P1 state */
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if (((Max_fid & 0x1) != 0) && ((Max_fid - 0x1) >= (Min_fid + 0x8))) { /* odd value */
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/* if odd value */
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if (((Max_fid & 0x1) != 0) && ((Max_fid - 0x1) >= (Min_fid + 0x8))) {
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Pstate_fid[1] = Max_fid - 0x1;
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Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800;
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Cur_fid = Pstate_fid[1];
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Cur_feq = Pstate_feq[1];
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if (((Pstate_vid[0] & 0x1) != 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* odd value */
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/* if odd value */
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if (((Pstate_vid[0] & 0x1) != 0) &&
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((Pstate_vid[0] - 0x1) < Min_vid)) {
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Pstate_vid[1] = Pstate_vid[0] + 0x1;
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Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
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Pstate_power[1] =
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((unsigned long long)Pstate_power[0] *
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Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1]) /
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((unsigned long long)Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
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((unsigned long long)Pstate_feq[0] *
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Pstate_volt[0] *
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Pstate_volt[0]);
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}
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if (((Pstate_vid[0] & 0x1) == 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* even value */
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/* if even value */
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if (((Pstate_vid[0] & 0x1) == 0) &&
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((Pstate_vid[0] - 0x1) < Min_vid)) {
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Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef;
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Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
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Pstate_power[1] =
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((unsigned long long)Pstate_power[0] *
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Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1]) /
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((unsigned long long)Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
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((unsigned long long)Pstate_feq[0] *
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Pstate_volt[0] *
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Pstate_volt[0]);
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}
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Pstate_num++;
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}
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if (((Max_fid & 0x1) == 0) && ((Max_fid - 0x2) >= (Min_fid + 0x8))) { /* even value */
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/* if even value */
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if (((Max_fid & 0x1) == 0) && ((Max_fid - 0x2) >= (Min_fid + 0x8))) {
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Pstate_fid[1] = Max_fid - 0x2;
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Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800;
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Cur_fid = Pstate_fid[1];
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Cur_feq = Pstate_feq[1];
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if (((Pstate_vid[0] & 0x1) != 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* odd value */
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/* if odd value */
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if (((Pstate_vid[0] & 0x1) != 0) &&
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((Pstate_vid[0] - 0x1) < Min_vid)) {
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Pstate_vid[1] = Pstate_vid[0] + 0x1;
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Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
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Pstate_power[1] =
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((unsigned long long)Pstate_power[0] *
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Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1]) /
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((unsigned long long)Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
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((unsigned long long)Pstate_feq[0] *
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Pstate_volt[0] *
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Pstate_volt[0]);
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}
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if (((Pstate_vid[0] & 0x1) == 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* even value */
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/* if even value */
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if (((Pstate_vid[0] & 0x1) == 0) &&
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((Pstate_vid[0] - 0x1) < Min_vid)) {
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Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef;
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Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
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Pstate_power[1] =
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((unsigned long long)Pstate_power[0] *
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Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1]) /
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((unsigned long long)Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
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((unsigned long long)Pstate_feq[0] *
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Pstate_volt[0] *
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Pstate_volt[0]);
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}
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Pstate_num++;
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@ -319,8 +343,10 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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1550 - Pstate_vid[Pstate_num] * 25;
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Pstate_power[Pstate_num] =
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((unsigned long long)Pstate_power[0] *
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Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] * Pstate_volt[Pstate_num]) /
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((unsigned long long)Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
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Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
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Pstate_volt[Pstate_num]) /
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((unsigned long long)Pstate_feq[0] *
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Pstate_volt[0] * Pstate_volt[0]);
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}
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Pstate_num++;
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}
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@ -335,8 +361,10 @@ nointpstatesup:
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Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25;
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Pstate_power[Pstate_num] =
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((unsigned long long)Pstate_power[0] *
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Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] * Pstate_volt[Pstate_num]) /
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((unsigned long long)Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
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Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
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Pstate_volt[Pstate_num]) /
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((unsigned long long)Pstate_feq[0] * Pstate_volt[0] *
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Pstate_volt[0]);
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Pstate_num++;
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} else {
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Pstate_fid[Pstate_num] = Start_fid;
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@ -346,8 +374,10 @@ nointpstatesup:
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Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25;
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Pstate_power[Pstate_num] =
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((unsigned long long)Pstate_power[0] *
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Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] * Pstate_volt[Pstate_num]) /
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((unsigned long long)Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
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Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
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Pstate_volt[Pstate_num]) /
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((unsigned long long)Pstate_feq[0] * Pstate_volt[0] *
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Pstate_volt[0]);
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Pstate_num++;
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}
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@ -356,7 +386,8 @@ nointpstatesup:
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for (index = 0; index < Pstate_num; index++) {
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printk(BIOS_INFO, "Pstate_freq[%d] = %dMHz\t", index,
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Pstate_feq[index]);
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printk(BIOS_INFO, "Pstate_vid[%d] = %d\t", index, Pstate_vid[index]);
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printk(BIOS_INFO, "Pstate_vid[%d] = %d\t",
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index, Pstate_vid[index]);
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printk(BIOS_INFO, "Pstate_volt[%d] = %dmv\t", index,
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Pstate_volt[index]);
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printk(BIOS_INFO, "Pstate_power[%d] = %dmw\n", index,
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@ -412,13 +443,21 @@ struct pstate {
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};
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struct cpuentry {
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uint16_t modelnr; /* numeric model value, unused in code */
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uint8_t brandID; /* CPUID 8000_0001h EBX [11:6] (BrandID) */
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uint32_t cpuid; /* CPUID 8000_0001h EAX [31:0] (CPUID) */
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uint8_t maxFID; /* FID/VID Status MaxFID Field */
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uint8_t startFID; /* FID/VID Status StartFID Field */
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uint16_t pwr:12; /* Thermal Design Power of Max P-State *10 (fixed point) */
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/* Other MAX P state are read from CPU, other P states in following table */
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/* numeric model value, unused in code */
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uint16_t modelnr;
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/* CPUID 8000_0001h EBX [11:6] (BrandID) */
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uint8_t brandID;
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/* CPUID 8000_0001h EAX [31:0] (CPUID) */
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uint32_t cpuid;
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/* FID/VID Status MaxFID Field */
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uint8_t maxFID;
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/* FID/VID Status StartFID Field */
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uint8_t startFID;
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/* Thermal Design Power of Max P-State *10 (fixed point) */
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uint16_t pwr:12;
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/* Other MAX P state are read from CPU,
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* other P states in following table
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*/
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struct pstate pstates[MAXP];
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};
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@ -427,335 +466,345 @@ struct cpuentry entr[] = {
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{152, 0xc, 0x20f51, 0x12, 0x12, 926,
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{{2400, 1350, 900}, {2200, 1300, 766},
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{2000, 1250, 651}, {1800, 1200, 522},
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{1000, 1100, 320}}},
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{1000, 1100, 320} } },
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{252, 0x10, 0x20f51, 0x12, 0x12, 926,
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{{2400, 1350, 900}, {2200, 1300, 766},
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{2000, 1250, 651}, {1800, 1200, 522},
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{1000, 1100, 320}}},
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{1000, 1100, 320} } },
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{852, 0x14, 0x20f51, 0x12, 0x12, 926,
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{{2400, 1350, 900}, {2200, 1300, 766},
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{2000, 1250, 651}, {1800, 1200, 522},
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{1000, 1100, 320}}},
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{1000, 1100, 320} } },
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{254, 0x10, 0x20f51, 0x14, 0x14, 926,
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{{2600, 1350, 902}, {2400, 1300, 770},
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{2200, 1250, 657}, {2000, 1200, 559},
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{1800, 1150, 476}, {1000, 1100, 361}}},
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{1800, 1150, 476}, {1000, 1100, 361} } },
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{854, 0x14, 0x20f51, 0x14, 0x14, 926,
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{{2600, 1350, 902}, {2400, 1300, 770},
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{2200, 1250, 657}, {2000, 1200, 559},
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{1800, 1150, 476}, {1000, 1100, 361}}},
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{1800, 1150, 476}, {1000, 1100, 361} } },
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{242, 0x10, 0x20f51, 0x8, 0x8, 853,
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{}},
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{} },
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{842, 0x10, 0x20f51, 0x8, 0x8, 853,
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{}},
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{} },
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{244, 0x10, 0x20f51, 0xa, 0xa, 853,
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{{1000, 1100, 378}}},
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{{1000, 1100, 378} } },
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{844, 0x14, 0x20f51, 0xa, 0xa, 853,
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{{1000, 1100, 378}}},
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{{1000, 1100, 378} } },
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{246, 0x10, 0x20f51, 0xc, 0xc, 853,
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{{1800, 1350, 853},
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{1000, 1100, 378}}},
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{1000, 1100, 378} } },
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{846, 0x14, 0x20f51, 0xc, 0xc, 853,
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{{1800, 1350, 853},
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{1000, 1100, 378}}},
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{1000, 1100, 378} } },
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{242, 0x10, 0x20f51, 0x8, 0x8, 853,
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{}},
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{} },
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{842, 0x14, 0x20f51, 0x8, 0x8, 853,
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{}},
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{} },
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{244, 0x10, 0x20f51, 0xa, 0xa, 853,
|
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{{1000, 1100, 378}}},
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{{1000, 1100, 378} } },
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{844, 0x14, 0x20f51, 0xa, 0xa, 853,
|
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{{1000, 1100, 378}}},
|
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{{1000, 1100, 378} } },
|
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{246, 0x10, 0x20f51, 0xc, 0xc, 853,
|
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{{1800, 1350, 827}, {1000, 1100, 366}}},
|
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{{1800, 1350, 827}, {1000, 1100, 366} } },
|
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{846, 0x14, 0x20f51, 0xc, 0xc, 853,
|
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{{1800, 1350, 827}, {1000, 1100, 366}}},
|
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{{1800, 1350, 827}, {1000, 1100, 366} } },
|
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{248, 0x10, 0x20f51, 0xe, 0xe, 853,
|
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{{2000, 1350, 827}, {1800, 1300, 700},
|
||||
{1000, 1100, 366}}},
|
||||
{1000, 1100, 366} } },
|
||||
{848, 0x14, 0x20f51, 0xe, 0xe, 853,
|
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{{2000, 1350, 827}, {1800, 1300, 700},
|
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{1000, 1100, 366}}},
|
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{1000, 1100, 366} } },
|
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{250, 0x10, 0x20f51, 0x10, 0x10, 853,
|
||||
{{2200, 1350, 853}, {2000, 1300, 827},
|
||||
{1800, 1250, 702}, {1000, 1100, 301}}},
|
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{1800, 1250, 702}, {1000, 1100, 301} } },
|
||||
{850, 0x14, 0x20f51, 0x10, 0x10, 853,
|
||||
{{2200, 1350, 853}, {2000, 1300, 827},
|
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{1800, 1250, 702}, {1000, 1100, 301}}},
|
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{1800, 1250, 702}, {1000, 1100, 301} } },
|
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/* OSA248CEP5AU */
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{248, 0x10, 0x00f5a, 0xe, 0xe, 890,
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{{2000, 1400, 700}, {1800, 1300, 470},
|
||||
{1000, 1200, 280}}},
|
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{1000, 1200, 280} } },
|
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/* begin OSK246FAA5BL */
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{246, 0x12, 0x20f51, 0xc, 0xc, 547,
|
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{{1800, 1350, 461}, {1000, 1100, 223}}},
|
||||
{{1800, 1350, 461}, {1000, 1100, 223} } },
|
||||
{846, 0x16, 0x20f51, 0xc, 0xc, 547,
|
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{{1800, 1350, 461}, {1000, 1100, 223}}},
|
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{{1800, 1350, 461}, {1000, 1100, 223} } },
|
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{148, 0xe, 0x20f51, 0xe, 0xe, 547,
|
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{{2000, 1350, 521}, {1800, 1300, 459},
|
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{1000, 1100, 211}}},
|
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{1000, 1100, 211} } },
|
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{248, 0x12, 0x20f51, 0xe, 0xe, 547,
|
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{{2000, 1350, 521}, {1800, 1300, 459},
|
||||
{1000, 1100, 211}}},
|
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{1000, 1100, 211} } },
|
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{848, 0x16, 0x20f51, 0xe, 0xe, 547,
|
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{{2000, 1350, 521}, {1800, 1300, 459},
|
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{1000, 1100, 211}}},
|
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{1000, 1100, 211} } },
|
||||
{250, 0x12, 0x20f51, 0x10, 0x10, 547,
|
||||
{{2200, 1350, 521}, {2000, 1300, 440},
|
||||
{1800, 1250, 379}, {1000, 1100, 199}}},
|
||||
{1800, 1250, 379}, {1000, 1100, 199} } },
|
||||
{850, 0x16, 0x20f51, 0x10, 0x10, 547,
|
||||
{{2200, 1350, 521}, {2000, 1300, 440},
|
||||
{1800, 1250, 379}, {1000, 1100, 199}}},
|
||||
{1800, 1250, 379}, {1000, 1100, 199} } },
|
||||
{144, 0xc, 0x20f71, 0xa, 0xa, 670,
|
||||
{{1000, 1100, 296}}},
|
||||
{{1000, 1100, 296} } },
|
||||
{148, 0xc, 0x20f71, 0xe, 0xe, 853,
|
||||
{{2000, 1350, 830}, {1800, 1300, 704},
|
||||
{1000, 1100, 296}}},
|
||||
{1000, 1100, 296} } },
|
||||
{152, 0xc, 0x20f71, 0x12, 0x12, 104,
|
||||
{{2400, 1350, 1016}, {2200, 1300, 863},
|
||||
{2000, 1250, 732}, {1800, 1200, 621},
|
||||
{1000, 1100, 419}}},
|
||||
{1000, 1100, 419} } },
|
||||
{146, 0xc, 0x20f71, 0xc, 0xc, 670,
|
||||
{{1800, 1350, 647}, {1000, 1100, 286}}},
|
||||
{{1800, 1350, 647}, {1000, 1100, 286} } },
|
||||
{150, 0xc, 0x20f71, 0x10, 0x10, 853,
|
||||
{{2200, 1350, 830}, {2000, 1300, 706},
|
||||
{1800, 1250, 596}, {1000, 1100, 350}}},
|
||||
{1800, 1250, 596}, {1000, 1100, 350} } },
|
||||
{154, 0xc, 0x20f71, 0x14, 0x14, 1040,
|
||||
{{2600, 1350, 1017}, {2400, 1300, 868},
|
||||
{2200, 1250, 740}, {2000, 1200, 630},
|
||||
{1800, 1150, 537}, {1000, 1100, 416}}},
|
||||
{1800, 1150, 537}, {1000, 1100, 416} } },
|
||||
/* rev E dualcore */
|
||||
{165, 0x2c, 0x20f12, 0xa, 0xa, 950,
|
||||
{{1000, 1100, 406}}},
|
||||
{{1000, 1100, 406} } },
|
||||
{265, 0x30, 0x20f12, 0xa, 0xa, 950,
|
||||
{{1000, 1100, 406}}},
|
||||
{{1000, 1100, 406} } },
|
||||
{865, 0x34, 0x20f12, 0xa, 0xa, 950,
|
||||
{{1000, 1100, 406}}},
|
||||
{{1000, 1100, 406} } },
|
||||
{270, 0x30, 0x20f12, 0xc, 0xc, 950,
|
||||
{{1800, 1300, 903}, {1000, 1100, 383}}},
|
||||
{{1800, 1300, 903}, {1000, 1100, 383} } },
|
||||
{870, 0x34, 0x20f12, 0xc, 0xc, 950,
|
||||
{{1800, 1300, 903}, {1000, 1100, 383}}},
|
||||
{{1800, 1300, 903}, {1000, 1100, 383} } },
|
||||
{275, 0x30, 0x20f12, 0xe, 0xe, 950,
|
||||
{{2000, 1300, 903}, {1800, 1250, 759},
|
||||
{1000, 1100, 361}}},
|
||||
{1000, 1100, 361} } },
|
||||
{875, 0x34, 0x20f12, 0xe, 0xe, 950,
|
||||
{{2000, 1300, 903}, {1800, 1250, 759},
|
||||
{1000, 1100, 361}}},
|
||||
{1000, 1100, 361} } },
|
||||
{280, 0x30, 0x20f12, 0x10, 0x10, 926,
|
||||
{{2400, 1350, 900}, {2200, 1300, 766},
|
||||
{1800, 1200, 552}, {1000, 1100, 320}}},
|
||||
{1800, 1200, 552}, {1000, 1100, 320} } },
|
||||
{880, 0x34, 0x20f12, 0x10, 0x10, 926,
|
||||
{{2400, 1350, 900}, {2200, 1300, 766},
|
||||
{1800, 1200, 552}, {1000, 1100, 320}}},
|
||||
{1800, 1200, 552}, {1000, 1100, 320} } },
|
||||
{170, 0x2c, 0x20f32, 0xc, 0xc, 1100,
|
||||
{{1800, 1300, 1056}, {1000, 1100, 514}}},
|
||||
{{1800, 1300, 1056}, {1000, 1100, 514} } },
|
||||
{175, 0x2c, 0x20f32, 0xe, 0xe, 1100,
|
||||
{{2000, 1300, 1056}, {1800, 1250, 891},
|
||||
{1000, 1100, 490}}},
|
||||
{1000, 1100, 490} } },
|
||||
{260, 0x32, 0x20f32, 0x8, 0x8, 550,
|
||||
{}},
|
||||
{} },
|
||||
{860, 0x36, 0x20f32, 0x8, 0x8, 550,
|
||||
{}},
|
||||
{} },
|
||||
{165, 0x2e, 0x20f32, 0xa, 0xa, 550,
|
||||
{{1000, 1100, 365}}},
|
||||
{{1000, 1100, 365} } },
|
||||
{265, 0x32, 0x20f32, 0xa, 0xa, 550,
|
||||
{{1000, 1100, 365}}},
|
||||
{{1000, 1100, 365} } },
|
||||
{865, 0x36, 0x20f32, 0xa, 0xa, 550,
|
||||
{{1000, 1100, 365}}},
|
||||
{{1000, 1100, 365} } },
|
||||
{270, 0x32, 0x20f12, 0xc, 0xc, 550,
|
||||
{{1800, 1150, 520}, {1000, 1100, 335}}},
|
||||
{{1800, 1150, 520}, {1000, 1100, 335} } },
|
||||
{870, 0x36, 0x20f12, 0xc, 0xc, 550,
|
||||
{{1800, 1150, 520}, {1000, 1100, 335}}},
|
||||
{{1800, 1150, 520}, {1000, 1100, 335} } },
|
||||
{180, 0x2c, 0x20f32, 0x10, 0x10, 1100,
|
||||
{{2200, 1300, 1056}, {2000, 1250, 891},
|
||||
{1800, 1200, 748}, {1000, 1100, 466}}},
|
||||
{1800, 1200, 748}, {1000, 1100, 466} } },
|
||||
/* OSP280 */
|
||||
{280, 0x31, 0x20f12, 0x10, 0x10, 680,
|
||||
{{2200, 1250, 650}, {2000, 1200, 574},
|
||||
{1800, 1150, 433}, {1000, 1100, 220}}},
|
||||
{1800, 1150, 433}, {1000, 1100, 220} } },
|
||||
/* AMA3000BEX5AR */
|
||||
{3000, 0x4, 0xf4a, 0xa, 0x0, 815,
|
||||
{{1600, 1400, 570}, {800, 1100, 190}}},
|
||||
{{1600, 1400, 570}, {800, 1100, 190} } },
|
||||
/* TMDML34BKX5LD, needs real TDP info */
|
||||
{34, 0xa, 0x20f42, 0xa, 0x0, 350,
|
||||
{{1600, 1400, 340}, {800, 1000, 330}}},
|
||||
{{1600, 1400, 340}, {800, 1000, 330} } },
|
||||
/* ADA3200AIO4BX */
|
||||
{3200, 0x4, 0x20fc2, 0xe, 0xe, 670,
|
||||
{{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275}}},
|
||||
{{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275} } },
|
||||
/* ADA2800AEP4AP */
|
||||
{2800, 0x4, 0xf48, 0xa, 0xa, 890,
|
||||
{{800, 1300, 350}}},
|
||||
{{800, 1300, 350} } },
|
||||
/* ADA3000AEP4AP */
|
||||
{3000, 0x4, 0xf48, 0xc, 0xc, 890,
|
||||
{{1800, 1400, 660}, {800, 1300, 350}}},
|
||||
{{1800, 1400, 660}, {800, 1300, 350} } },
|
||||
/* ADA3200AEP5AP */
|
||||
{3200, 0x4, 0xf48, 0xc, 0xc, 890,
|
||||
{{1800, 1400, 660}, {800, 1300, 350}}},
|
||||
{{1800, 1400, 660}, {800, 1300, 350} } },
|
||||
/* ADA3400AEP5AP */
|
||||
{3400, 0x4, 0xf48, 0xe, 0xe, 890,
|
||||
{{2000, 1400, 700}, {800, 1300, 350}}},
|
||||
{{2000, 1400, 700}, {800, 1300, 350} } },
|
||||
/* ADA2800AEP4AR */
|
||||
{2800, 0x4, 0xf4a, 0xa, 0xa, 890,
|
||||
{{1000, 1100, 220}}},
|
||||
{{1000, 1100, 220} } },
|
||||
/* ADA3000AEP4AR */
|
||||
{3000, 0x4, 0xf4a, 0xc, 0xc, 890,
|
||||
{{1800, 1400, 660}, {1000, 1100, 220}}},
|
||||
{{1800, 1400, 660}, {1000, 1100, 220} } },
|
||||
/* ADA3700AEP5AR */
|
||||
{3700, 0x4, 0xf4a, 0x10, 0x10, 890,
|
||||
{{2200, 1400, 720}, {2000, 1300, 530}, {1800, 1200, 390}, {1000, 1100, 220}}},
|
||||
{{2200, 1400, 720}, {2000, 1300, 530},
|
||||
{1800, 1200, 390}, {1000, 1100, 220} } },
|
||||
/* ADA2800AEP4AX */
|
||||
{2800, 0x4, 0xfc0, 0xa, 0xa, 890,
|
||||
{{1000, 1100, 220}}},
|
||||
{{1000, 1100, 220} } },
|
||||
/* ADA3000AEP4AX */
|
||||
{3000, 0x4, 0xfc0, 0xc, 0xc, 890,
|
||||
{{1800, 1400, 670}, {1000, 1100, 220}}},
|
||||
{{1800, 1400, 670}, {1000, 1100, 220} } },
|
||||
/* ADA3200AEP4AX */
|
||||
{3200, 0x4, 0xfc0, 0xe, 0xe, 890,
|
||||
{{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220}}},
|
||||
{{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220} } },
|
||||
/* ADA3400AEP4AX */
|
||||
{3400, 0x4, 0xfc0, 0x10, 0x10, 890,
|
||||
{{2200, 1400, 720}, {2000, 1300, 530}, {1800, 1200, 390}, {1000, 1100, 220}}},
|
||||
{{2200, 1400, 720}, {2000, 1300, 530},
|
||||
{1800, 1200, 390}, {1000, 1100, 220} } },
|
||||
/* ADA3500DEP4AS */
|
||||
{3500, 0x4, 0xf7a, 0xe, 0xe, 890,
|
||||
{{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220}}},
|
||||
{{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220} } },
|
||||
/* ADA3500DEP4AW */
|
||||
{3500, 0x4, 0xff0, 0xe, 0xe, 890,
|
||||
{{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220}}},
|
||||
{{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220} } },
|
||||
/* ADA3800DEP4AW */
|
||||
{3800, 0x4, 0xff0, 0x10, 0x10, 890,
|
||||
{{2200, 1400, 720}, {2000, 1300, 530}, {1800, 1200, 390}, {1000, 1100, 220}}},
|
||||
{{2200, 1400, 720}, {2000, 1300, 530},
|
||||
{1800, 1200, 390}, {1000, 1100, 220} } },
|
||||
/* ADA4000DEP5AS */
|
||||
{4000, 0x4, 0xf7a, 0x10, 0x10, 890,
|
||||
{{2200, 1400, 720}, {2000, 1300, 530}, {1800, 1200, 390}, {1000, 1100, 220}}},
|
||||
{{2200, 1400, 720}, {2000, 1300, 530},
|
||||
{1800, 1200, 390}, {1000, 1100, 220} } },
|
||||
/* ADA3500DAA4BN */
|
||||
{3500, 0x4, 0x20f71, 0xe, 0xe, 670,
|
||||
{{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275}}},
|
||||
{{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275} } },
|
||||
/* ADA3700DAA5BN */
|
||||
{3700, 0x4, 0x20f71, 0xe, 0xe, 853,
|
||||
{{2000, 1350, 830}, {1800, 1300, 704}, {1000, 1100, 361}}},
|
||||
{{2000, 1350, 830}, {1800, 1300, 704}, {1000, 1100, 361} } },
|
||||
/* ADA4000DAA5BN */
|
||||
{4000, 0x4, 0x20f71, 0x10, 0x10, 853,
|
||||
{{2200, 1350, 830}, {2000, 1300, 706}, {1800, 1250, 596}, {1000, 1100, 350}}},
|
||||
{{2200, 1350, 830}, {2000, 1300, 706},
|
||||
{1800, 1250, 596}, {1000, 1100, 350} } },
|
||||
/* ADA3700DKA5CF */
|
||||
{3700, 0x4, 0x30f72, 0xe, 0xe, 853,
|
||||
{{2000, 1350, 830}, {1800, 1300, 704}, {1000, 1100, 361}}},
|
||||
{{2000, 1350, 830}, {1800, 1300, 704}, {1000, 1100, 361} } },
|
||||
/* ADA4000DKA5CF */
|
||||
{4000, 0x4, 0x30f72, 0x10, 0x10, 853,
|
||||
{{2200, 1350, 830}, {2000, 1300, 706}, {1800, 1250, 596}, {1000, 1100, 350}}},
|
||||
{{2200, 1350, 830}, {2000, 1300, 706},
|
||||
{1800, 1250, 596}, {1000, 1100, 350} } },
|
||||
/* ADA3800DAA4BP */
|
||||
{3800, 0x4, 0x20ff0, 0x10, 0x10, 853,
|
||||
{{2200, 1350, 830}, {2000, 1300, 706}, {1800, 1250, 596}, {1000, 1100, 350}}},
|
||||
{{2200, 1350, 830}, {2000, 1300, 706},
|
||||
{1800, 1250, 596}, {1000, 1100, 350} } },
|
||||
/* ADA3000DIK4BI */
|
||||
{3000, 0x4, 0x10ff0, 0xa, 0xa, 670,
|
||||
{{1000, 1100, 210}}},
|
||||
{{1000, 1100, 210} } },
|
||||
/* ADA3200DIK4BI */
|
||||
{3200, 0x4, 0x10ff0, 0xc, 0xc, 670,
|
||||
{{1800, 1350, 560}, {1000, 1100, 210}}},
|
||||
{{1800, 1350, 560}, {1000, 1100, 210} } },
|
||||
/* ADA3500DIK4BI */
|
||||
{3500, 0x4, 0x10ff0, 0xe, 0xe, 670,
|
||||
{{2000, 1350, 560}, {1800, 1300, 460}, {1000, 1100, 200}}},
|
||||
{{2000, 1350, 560}, {1800, 1300, 460}, {1000, 1100, 200} } },
|
||||
/* ADA3000DAA4BP */
|
||||
{3000, 0x4, 0x20ff0, 0xa, 0xa, 670,
|
||||
{{1000, 1100, 296}}},
|
||||
{{1000, 1100, 296} } },
|
||||
/* ADA3200DAA4BP */
|
||||
{3200, 0x4, 0x20ff0, 0xc, 0xc, 670,
|
||||
{{1800, 1350, 647}, {1000, 1100, 286}}},
|
||||
{{1800, 1350, 647}, {1000, 1100, 286} } },
|
||||
/* ADA3500DAA4BP */
|
||||
{3500, 0x4, 0x20ff0, 0xe, 0xe, 670,
|
||||
{{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275}}},
|
||||
{{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275} } },
|
||||
/* ADA3000DAA4BW */
|
||||
{3000, 0x4, 0x20ff2, 0xa, 0xa, 670,
|
||||
{{1000, 1100, 296}}},
|
||||
{{1000, 1100, 296} } },
|
||||
/* ADA3200DAA4BW */
|
||||
{3200, 0x4, 0x20ff2, 0xc, 0xc, 670,
|
||||
{{1800, 1350, 647}, {1000, 1100, 286}}},
|
||||
{{1800, 1350, 647}, {1000, 1100, 286} } },
|
||||
/* ADA3500DAA4BW */
|
||||
{3500, 0x4, 0x20ff2, 0xe, 0xe, 670,
|
||||
{{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275}}},
|
||||
{{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275} } },
|
||||
/* ADA3200DKA4CG */
|
||||
{3200, 0x4, 0x30ff2, 0xc, 0xc, 670,
|
||||
{{1800, 1350, 647}, {1000, 1100, 286}}},
|
||||
{{1800, 1350, 647}, {1000, 1100, 286} } },
|
||||
/* ADA3800DAA4BW */
|
||||
{3800, 0x4, 0x20ff2, 0x10, 0x10, 853,
|
||||
{{2200, 1350, 830}, {2000, 1300, 706}, {1800, 1250, 596}, {1000, 1100, 350}}},
|
||||
{{2200, 1350, 830}, {2000, 1300, 706},
|
||||
{1800, 1250, 596}, {1000, 1100, 350} } },
|
||||
/* ADA3000AIK4BX */
|
||||
{3000, 0x4, 0x20fc2, 0xc, 0xc, 510,
|
||||
{{1800, 1350, 428}, {1000, 1100, 189}}},
|
||||
{{1800, 1350, 428}, {1000, 1100, 189} } },
|
||||
/* ADAFX53DEP5AS */
|
||||
{53, 0x24, 0xf7a, 0x2a, 0x10, 890,
|
||||
{{1200, 1100, 250}}},
|
||||
{{1200, 1100, 250} } },
|
||||
/* ADAFX55DEI5AS */
|
||||
{55, 0x24, 0xf7a, 0x2a, 0x12, 1040,
|
||||
{{1200, 1100, 250}}},
|
||||
{{1200, 1100, 250} } },
|
||||
/* ADAFX55DAA5BN */
|
||||
{55, 0x24, 0x20f71, 0x2a, 0x12, 1040,
|
||||
{{1200, 1100, 422}}},
|
||||
{{1200, 1100, 422} } },
|
||||
/* ADAFX57DAA5BN */
|
||||
{57, 0x24, 0x20f71, 0x2a, 0x14, 1040,
|
||||
{{1200, 1100, 434}}},
|
||||
{{1200, 1100, 434} } },
|
||||
/* SDA3100AIP3AX */
|
||||
{3100, 0x22, 0xfc0, 0xa, 0xa, 620,
|
||||
{{1000, 1100, 200}}},
|
||||
{{1000, 1100, 200} } },
|
||||
/* SDA2600AIO2BA */
|
||||
{2600, 0x22, 0x10fc0, 0x8, 0x8, 590,
|
||||
{}},
|
||||
{} },
|
||||
/* SDA2800AIO3BA */
|
||||
{2800, 0x22, 0x10fc0, 0x8, 0x8, 590,
|
||||
{}},
|
||||
{} },
|
||||
/* SDA3000AIO2BA */
|
||||
{3000, 0x22, 0x10fc0, 0xa, 0xa, 590,
|
||||
{{1000, 1100, 190}}},
|
||||
{{1000, 1100, 190} } },
|
||||
/* SDA3100AIO3BA */
|
||||
{3100, 0x22, 0x10fc0, 0xa, 0xa, 590,
|
||||
{{1000, 1100, 190}}},
|
||||
{{1000, 1100, 190} } },
|
||||
/* SDA3300AIO2BA */
|
||||
{3300, 0x22, 0x10fc0, 0xc, 0xc, 590,
|
||||
{{1800, 1350, 488}, {1000, 1100, 180}}},
|
||||
{{1800, 1350, 488}, {1000, 1100, 180} } },
|
||||
/* SDA2500AIO3BX */
|
||||
{2500, 0x26, 0x20fc2, 0x6, 0x6, 590,
|
||||
{}},
|
||||
{} },
|
||||
/* SDA2600AIO2BX */
|
||||
{2600, 0x26, 0x20fc2, 0x8, 0x8, 590,
|
||||
{}},
|
||||
{} },
|
||||
/* SDA2800AIO3BX */
|
||||
{2800, 0x26, 0x20fc2, 0x8, 0x8, 590,
|
||||
{}},
|
||||
{} },
|
||||
/* SDA3000AIO2BX */
|
||||
{3000, 0x26, 0x20fc2, 0xa, 0xa, 590,
|
||||
{{1000, 1100, 217}}},
|
||||
{{1000, 1100, 217} } },
|
||||
/* SDA3100AIO3BX */
|
||||
{3100, 0x26, 0x20fc2, 0xa, 0xa, 590,
|
||||
{{1000, 1100, 217}}},
|
||||
{{1000, 1100, 217} } },
|
||||
/* SDA3300AIO2BX */
|
||||
{3300, 0x26, 0x20fc2, 0xc, 0xc, 590,
|
||||
{{1800, 1350, 496}, {1000, 1100, 207}}},
|
||||
{{1800, 1350, 496}, {1000, 1100, 207} } },
|
||||
/* SDA3400AIO3BX */
|
||||
{3400, 0x26, 0x20fc2, 0xc, 0xc, 590,
|
||||
{{1800, 1350, 496}, {1000, 1100, 207}}},
|
||||
{{1800, 1350, 496}, {1000, 1100, 207} } },
|
||||
/* TMSMT32BQX4LD */
|
||||
{32, 0xb, 0x20f42, 0xa, 0x0, 240,
|
||||
{{1600, 1150, 199}, {800, 900, 77}}},
|
||||
{{1600, 1150, 199}, {800, 900, 77} } },
|
||||
/* TMSMT34BQX5LD */
|
||||
{34, 0xb, 0x20f42, 0xa, 0x0, 240,
|
||||
{{1600, 1150, 199}, {800, 900, 79}}},
|
||||
{{1600, 1150, 199}, {800, 900, 79} } },
|
||||
/* TMSMT37BQX5LD */
|
||||
{37, 0xb, 0x20f42, 0xc, 0x0, 250,
|
||||
{{1800, 1150, 209}, {1600, 1100, 175}, {800, 900, 79}}},
|
||||
{{1800, 1150, 209}, {1600, 1100, 175}, {800, 900, 79} } },
|
||||
/* ADA4400DAA6CD */
|
||||
{4400, 0x5, 0x20f32, 0xe, 0xe, 1100,
|
||||
{{2000, 1300, 1056}, {1800, 1250, 891}, {1000, 1100, 490}}},
|
||||
{{2000, 1300, 1056}, {1800, 1250, 891}, {1000, 1100, 490} } },
|
||||
/* ADA4800DAA6CD */
|
||||
{4800, 0x5, 0x20f32, 0x10, 0x10, 1100,
|
||||
{{2200, 1300, 1056}, {2000, 1250, 891}, {1800, 1200, 748}, {1000, 1100, 466}}},
|
||||
{{2200, 1300, 1056}, {2000, 1250, 891},
|
||||
{1800, 1200, 748}, {1000, 1100, 466} } },
|
||||
/* ADA3800DAA5BV */
|
||||
{3800, 0x5, 0x20fb1, 0xc, 0xc, 890,
|
||||
{{1800, 1300, 846}, {1000, 1100, 401}}},
|
||||
{{1800, 1300, 846}, {1000, 1100, 401} } },
|
||||
/* ADA4200DAA5BV */
|
||||
{4200, 0x5, 0x20fb1, 0xe, 0xe, 890,
|
||||
{{2000, 1300, 846}, {1800, 1250, 709}, {1000, 1100, 376}}},
|
||||
{{2000, 1300, 846}, {1800, 1250, 709}, {1000, 1100, 376} } },
|
||||
/* ADA4600DAA5BV */
|
||||
{4600, 0x5, 0x20fb1, 0x10, 0x10, 1100,
|
||||
{{2200, 1300, 1056}, {2000, 1250, 891}, {1800, 1200, 748}, {1000, 1100, 466}}},
|
||||
{{2200, 1300, 1056}, {2000, 1250, 891},
|
||||
{1800, 1200, 748}, {1000, 1100, 466} } },
|
||||
};
|
||||
|
||||
static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
|
||||
|
|
@ -775,7 +824,7 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
|
|||
|
||||
/* See if the CPUID(0x80000007) returned EDX[2:1]==11b */
|
||||
cpuid1 = cpuid(0x80000007);
|
||||
if ((cpuid1.edx & 0x6)!=0x6) {
|
||||
if ((cpuid1.edx & 0x6) != 0x6) {
|
||||
printk(BIOS_INFO, "Processor not capable of performing P-state transitions\n");
|
||||
return;
|
||||
}
|
||||
|
|
@ -799,7 +848,7 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
|
|||
if ((entr[i].cpuid == cpuid1.eax)
|
||||
&& (entr[i].startFID == Start_fid)
|
||||
&& (entr[i].maxFID == Max_fid)
|
||||
&& (entr[i].brandID == ((u8 )((cpuid1.ebx >> 6) & 0xff)))) {
|
||||
&& (entr[i].brandID == ((u8)((cpuid1.ebx >> 6) & 0xff)))) {
|
||||
data = &entr[i];
|
||||
break;
|
||||
}
|
||||
|
|
@ -846,16 +895,23 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
|
|||
Pstate_power[0] = data->pwr * 100;
|
||||
|
||||
for (Pstate_num = 1;
|
||||
(Pstate_num <= MAXP) && (data->pstates[Pstate_num - 1].freqMhz != 0);
|
||||
(Pstate_num <= MAXP) &&
|
||||
(data->pstates[Pstate_num - 1].freqMhz != 0);
|
||||
Pstate_num++) {
|
||||
Pstate_fid[Pstate_num] = freq_to_fid(data->pstates[Pstate_num - 1].freqMhz) & 0x3f;
|
||||
Pstate_feq[Pstate_num] = data->pstates[Pstate_num - 1].freqMhz;
|
||||
Pstate_vid[Pstate_num] = vid_to_reg(data->pstates[Pstate_num - 1].voltage);
|
||||
Pstate_power[Pstate_num] = data->pstates[Pstate_num - 1].tdp * 100;
|
||||
Pstate_fid[Pstate_num] =
|
||||
freq_to_fid(data->pstates[Pstate_num - 1].freqMhz) & 0x3f;
|
||||
Pstate_feq[Pstate_num] =
|
||||
data->pstates[Pstate_num - 1].freqMhz;
|
||||
Pstate_vid[Pstate_num] =
|
||||
vid_to_reg(data->pstates[Pstate_num - 1].voltage);
|
||||
Pstate_power[Pstate_num] =
|
||||
data->pstates[Pstate_num - 1].tdp * 100;
|
||||
}
|
||||
|
||||
for (i=0;i<Pstate_num;i++)
|
||||
printk(BIOS_DEBUG, "P#%d freq %d [MHz] voltage %d [mV] TDP %d [mW]\n", i,
|
||||
for (i = 0; i < Pstate_num; i++)
|
||||
printk(BIOS_DEBUG,
|
||||
"P#%d freq %d [MHz] voltage %d [mV] TDP %d [mW]\n",
|
||||
i,
|
||||
Pstate_feq[i],
|
||||
vid_from_reg(Pstate_vid[i]),
|
||||
Pstate_power[i]);
|
||||
|
|
@ -866,13 +922,14 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
|
|||
continue;
|
||||
|
||||
for (i = 0; i < (cmp_cap + 1); i++) {
|
||||
write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid,
|
||||
write_pstates_for_core(Pstate_num,
|
||||
Pstate_feq, Pstate_vid,
|
||||
Pstate_fid, Pstate_power, index+i,
|
||||
pcontrol_blk, plen, onlyBSP, control);
|
||||
}
|
||||
index += i;
|
||||
}
|
||||
printk(BIOS_DEBUG,"%d Processor objects emitted to SSDT\n",index);
|
||||
printk(BIOS_DEBUG, "%d Processor objects emitted to SSDT\n", index);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue