diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c
index c4d34a5301..b83e700e57 100644
--- a/src/soc/amd/picasso/fch.c
+++ b/src/soc/amd/picasso/fch.c
@@ -165,12 +165,12 @@ static void al2ahb_clock_gate(void)
 	uint8_t al2ahb_val;
 	uintptr_t al2ahb_base = ALINK_AHB_ADDRESS;
 
-	al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET));
+	al2ahb_val = read8p(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET);
 	al2ahb_val |= AL2AHB_CLK_GATE_EN;
-	write8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET), al2ahb_val);
-	al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET));
+	write8p(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET, al2ahb_val);
+	al2ahb_val = read8p(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET);
 	al2ahb_val |= AL2AHB_HCLK_GATE_EN;
-	write8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET), al2ahb_val);
+	write8p(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET, al2ahb_val);
 }
 
 /* configure the general purpose PCIe clock outputs according to the devicetree settings */