cpu/intel/smm/gen1: Deal with SMM save state compatibility
Change-Id: I92326e3e0481d750cb9c90f717ed748000e33ad3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@ -168,6 +168,9 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
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if (smm_reloc_params.ied_size)
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setup_ied_area(&smm_reloc_params);
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/* This may not be be correct for older CPU's supported by this code,
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but given that em64t101_smm_state_save_area_t is larger than the
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save_state of these CPU's it works. */
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*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
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}
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@ -191,6 +194,8 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
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{
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msr_t mtrr_cap;
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struct smm_relocation_params *relo_params = &smm_reloc_params;
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/* The em64t101 save state is sufficiently compatible with older
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save states with regards of smbase, smm_revision. */
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em64t101_smm_state_save_area_t *save_state;
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u32 smbase = staggered_smbase;
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u32 iedbase = relo_params->ied_base;
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@ -208,7 +213,10 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
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save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE -
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sizeof(*save_state));
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save_state->smbase = smbase;
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save_state->iedbase = iedbase;
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printk(BIOS_SPEW, "SMM revision: 0x%08x\n", save_state->smm_revision);
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if (save_state->smm_revision == 0x00030101)
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save_state->iedbase = iedbase;
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/* Write EMRR and SMRR MSRs based on indicated support. */
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mtrr_cap = rdmsr(MTRR_CAP_MSR);
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