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Intel i5000 board & chips: Remove - using LATE_CBMEM_INIT 

All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.

If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.

chips:
northbridge/intel/i5000

Mainboards:
mainboard/supermicro/x7db8
mainboard/asus/dsbf

Change-Id: I6614c0033b4439d196f26819998d3f85e6d11c00
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Martin Roth 2017-10-15 14:58:49 -06:00 committed by Martin Roth
parent 779b32beff
commit f6af8943e2
25 changed files with 0 additions and 3469 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/cpu/intel/Kconfig
View File

@ -39,7 +39,6 @@ source src/cpu/intel/socket_mPGA604/Kconfig
source src/cpu/intel/socket_PGA370/Kconfig
source src/cpu/intel/socket_441/Kconfig
source src/cpu/intel/socket_LGA1155/Kconfig
source src/cpu/intel/socket_LGA771/Kconfig
source src/cpu/intel/socket_LGA775/Kconfig
source src/cpu/intel/socket_rPGA988B/Kconfig
source src/cpu/intel/socket_rPGA989/Kconfig

1
src/cpu/intel/Makefile.inc
View File

@ -31,7 +31,6 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_model_406dx
subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2
subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA1155) += socket_LGA1155
subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA771) += socket_LGA771
subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775
#socket_mPGA604_533Mhz

18
src/cpu/intel/socket_LGA771/Kconfig
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@ -1,18 +0,0 @@
config CPU_INTEL_SOCKET_LGA771
bool
select CPU_INTEL_MODEL_6FX
select SSE2
select MMX
select AP_IN_SIPI_WAIT
if CPU_INTEL_SOCKET_LGA771
config DCACHE_RAM_BASE
hex
default 0xfefc0000
config DCACHE_RAM_SIZE
hex
default 0x8000
endif

12
src/cpu/intel/socket_LGA771/Makefile.inc
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@ -1,12 +0,0 @@
subdirs-y += ../model_6ex
subdirs-y += ../model_6fx
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
subdirs-y += ../hyperthreading
cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
romstage-y += ../car/romstage.c

34
src/mainboard/asus/dsbf/Kconfig
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@ -1,34 +0,0 @@
if BOARD_ASUS_DSBF
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_INTEL_SOCKET_LGA771
select SOUTHBRIDGE_INTEL_I3100
select NORTHBRIDGE_INTEL_I5000
select SUPERIO_WINBOND_W83627HF
select BOARD_ROMSIZE_KB_512
select HAVE_PIRQ_TABLE
select DRIVERS_I2C_W83793
select DRIVERS_GENERIC_IOAPIC
config MAINBOARD_DIR
string
default asus/dsbf
config MAINBOARD_PART_NUMBER
string
default "DSBF"
config MMCONF_BASE_ADDRESS
hex
default 0xe0000000
config IRQ_SLOT_COUNT
int
default 48
config MAX_CPUS
int
default 8
endif

2
src/mainboard/asus/dsbf/Kconfig.name
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@ -1,2 +0,0 @@
config BOARD_ASUS_DSBF
bool "DSBF"

1
src/mainboard/asus/dsbf/board_info.txt
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@ -1 +0,0 @@
Category: server

104
src/mainboard/asus/dsbf/cmos.layout
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@ -1,104 +0,0 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2007-2008 coresystems GmbH
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; version 2 of
# the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# -----------------------------------------------------------------
entries
# -----------------------------------------------------------------
# Status Register A
# -----------------------------------------------------------------
# Status Register B
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#390 2 r 0 unused?
# -----------------------------------------------------------------
# coreboot config options: console
#392 3 r 0 unused
395 4 e 6 debug_level
#399 1 r 0 unused
# coreboot config options: cpu
400 1 e 2 hyper_threading
#401 7 r 0 unused
# coreboot config options: southbridge
408 1 e 1 nmi
#409 2 e 7 power_on_after_fail
#411 5 r 0 unused
# coreboot config options: bootloader
416 512 s 0 boot_devices
928 8 h 0 boot_default
936 1 e 8 cmos_defaults_loaded
937 1 e 1 lpt
#938 46 r 0 unused
# coreboot config options: check sums
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 1 Emergency
6 2 Alert
6 3 Critical
6 4 Error
6 5 Warning
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Disable
7 1 Enable
7 2 Keep
8 0 No
8 1 Yes
9 0 Secondary
9 1 Primary
# -----------------------------------------------------------------
checksums
checksum 392 983 984

180
src/mainboard/asus/dsbf/devicetree.cb
View File

@ -1,180 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2009 coresystems GmbH
## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip northbridge/intel/i5000
device cpu_cluster 0 on
chip cpu/intel/socket_LGA771
device lapic 0 on end
end
end
device domain 0 on
device pci 00.0 on # Host bridge
subsystemid 0x1043 0x81db
end
device pci 02.0 on # PCI Express x8 Port 2-3
ioapic_irq 8 INTA 0x10
ioapic_irq 8 INTB 0x11
ioapic_irq 8 INTC 0x12
ioapic_irq 8 INTD 0x13
device pci 00.0 on # PCI Express Upstream Port
device pci 00.0 on # PCI Express Downstream Port E1
device pci 00.0 on # 6700PXH PCI Express-to-PCI Bridge A
ioapic_irq 8 INTA 0x11
ioapic_irq 8 INTB 0x10
ioapic_irq 8 INTC 0x11
ioapic_irq 8 INTD 0x10
# PCI slot
device pci 00.2 on # 6700PXH PCI Express-to-PCI Bridge B
# PCI slot
end
end
end
device pci 00.1 on end
device pci 00.3 on # PCI Express to PCI-X Bridge
ioapic_irq 9 INTA 3
ioapic_irq 9 INTB 0
ioapic_irq 9 INTC 1
ioapic_irq 9 INTD 2
# PCI-X Slot
end
end
end
device pci 03.0 on
ioapic_irq 8 INTA 0x10
end
device pci 04.0 on
ioapic_irq 8 INTA 0x10
end
device pci 05.0 on
ioapic_irq 8 INTA 0x10
end
device pci 06.0 on
ioapic_irq 8 INTA 0x10
end
device pci 07.0 on
ioapic_irq 8 INTA 0x10
end
device pci 10.0 on end # FBD
device pci 10.1 on end # FBD
device pci 10.2 on end # FBD
device pci 11.0 on end # FBD reserved
device pci 13.0 on end # FBD reserved
device pci 15.0 on end # FBD
device pci 16.0 on end # FBD
chip drivers/generic/ioapic
register "have_isa_interrupts" = "1"
register "irq_on_fsb" = "1"
register "enable_virtual_wire" = "1"
register "base" = "(void *)0xfec00000"
device ioapic 8 on end
end
chip drivers/generic/ioapic
register "irq_on_fsb" = "1"
register "base" = "(void *)0xfec80000"
device ioapic 9 on end
end
chip southbridge/intel/i3100
register "pirq_a_d" = "0x0b0b0b0b"
register "pirq_e_h" = "0x80808080"
register "sata_ports_implemented" = "0x3f"
device pci 1c.0 on
ioapic_irq 8 INTA 0x14
ioapic_irq 8 INTB 0x15
ioapic_irq 8 INTC 0x16
ioapic_irq 8 INTD 0x17
end # PCIe bridge
device pci 1d.0 on
ioapic_irq 8 INTA 0x10
end # USB UHCI
device pci 1d.1 on
ioapic_irq 8 INTB 0x11
end # USB UHCI
device pci 1d.2 on
ioapic_irq 8 INTC 0x12
end # USB UHCI
device pci 1d.3 on
ioapic_irq 8 INTD 0x13
end # USB UHCI
device pci 1d.7 on end # USB2 EHCI
device pci 1e.0 on
device pci 01.0 on end
end
device pci 1f.0 on # PCI-LPC bridge
ioapic_irq 8 INTA 0x11
chip superio/winbond/w83627hf
device pnp 2e.0 off end # FDC
device pnp 2e.1 on # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Serial Port 1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off end
device pnp 2e.5 on # KBC
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # Game port / MIDI
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 on end # GPIO3
device pnp 2e.a on end # ACPI
device pnp 2e.b off end # HWMON
end
end
device pci 1f.1 off end # IDE
device pci 1f.2 on end # SATA
device pci 1f.3 on # SMBUS
chip drivers/i2c/w83793
register "mfc" = "0x28"
register "fanin" = "0x1f"
register "peci_agent_conf" = "0x33"
register "tcase0" = "0x5e"
register "tcase1" = "0x5e"
register "tcase2" = "0x5e"
register "tcase3" = "0x5e"
register "tr_enable" = "0x01"
register "critical_temperature" = "0x7f"
register "td1_fan_select" = "0x09"
register "td2_fan_select" = "0x09"
register "td3_fan_select" = "0x09"
register "td4_fan_select" = "0x09"
register "tr1_fan_select" = "0x09"
register "tr2_fan_select" = "0x09"
device i2c 0x2f on end
end
end
end
end
end

53
src/mainboard/asus/dsbf/irq_tables.c
View File

@ -1,53 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/pirq_routing.h>
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x1f << 3) | 0x0, /* Interrupt router dev */
0, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */
0x2670, /* Device */
0, /* Miniport */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0, /* Checksum (has to be set to some value that
* would give 0 after the sum of all bytes
* for this structure (including checksum).
*/
{
/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, (0x1c << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
{0x00, (0x1c << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
{0x00, (0x1c << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0},
{0x00, (0x1c << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0},
{0x00, (0x1d << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
{0x00, (0x1d << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
{0x00, (0x1d << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0},
{0x00, (0x1d << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0},
{0x00, (0x1d << 3) | 0x7, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
{0x00, (0x1f << 3) | 0x1, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
{0x00, (0x1f << 3) | 0x2, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

139
src/mainboard/asus/dsbf/romstage.c
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@ -1,139 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <lib.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <northbridge/intel/i5000/raminit.h>
#include <northbridge/intel/i3100/i3100.h>
#include <southbridge/intel/i3100/i3100.h>
#include <southbridge/intel/i3100/early_smbus.c>
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
#define RCBA_RPC 0x0224 /* 32 bit */
#define RCBA_HPTC 0x3404 /* 32 bit */
#define RCBA_GCS 0x3410 /* 32 bit */
#define RCBA_FD 0x3418 /* 32 bit */
static void early_config(void)
{
u32 gcs, rpc, fd;
/* Enable RCBA */
pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
/* Disable watchdog */
gcs = read32(DEFAULT_RCBA + RCBA_GCS);
gcs |= (1 << 5); /* No reset */
write32(DEFAULT_RCBA + RCBA_GCS, gcs);
/* Configure PCIe port B as 4x */
rpc = read32(DEFAULT_RCBA + RCBA_RPC);
rpc |= (3 << 0);
write32(DEFAULT_RCBA + RCBA_RPC, rpc);
/* Disable Modem, Audio, PCIe ports 2/3/4 */
fd = read32(DEFAULT_RCBA + RCBA_FD);
fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);
write32(DEFAULT_RCBA + RCBA_FD, fd);
/* Enable HPET */
write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));
/* Setup sata mode */
pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40);
}
#define DEFAULT_GPIOBASE 0x1180
static void setup_gpio(void)
{
pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1);
pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4));
outl(0x1b0ce7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
outl(0xec00ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
outl(0xff350000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
outl(0x0000e742, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
outl(0x00000006, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
outl(0x00000300, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
outl(0x00030301, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */
}
static void i5000_lpc_config(void)
{
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
}
int mainboard_set_fbd_clock(int speed)
{
switch(speed) {
case 533:
smbus_write_byte(0x6f, 0x80, 0x21);
return 0;
case 667:
smbus_write_byte(0x6f, 0x80, 0x23);
return 0;
default:
printk(BIOS_ERR, "Invalid clock: %dMHz\n", speed);
die("");
return -1;
}
}
void mainboard_romstage_entry(unsigned long bist)
{
if (bist == 0)
enable_lapic();
i5000_lpc_config();
winbond_enable_serial(PNP_DEV(0x2e, 2), 0x3f8);
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
early_config();
setup_gpio();
enable_smbus();
smbus_write_byte(0x6f, 0x00, 0x63);
smbus_write_byte(0x6f, 0x01, 0x04);
smbus_write_byte(0x6f, 0x02, 0x53);
smbus_write_byte(0x6f, 0x03, 0x39);
smbus_write_byte(0x6f, 0x08, 0x06);
smbus_write_byte(0x6f, 0x09, 0x00);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1);
i5000_fbdimm_init();
smbus_write_byte(0x69, 0x01, 0x01);
}

34
src/mainboard/supermicro/x7db8/Kconfig
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@ -1,34 +0,0 @@
if BOARD_SUPERMICRO_X7DB8
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_INTEL_SOCKET_LGA771
select SOUTHBRIDGE_INTEL_I3100
select NORTHBRIDGE_INTEL_I5000
select SUPERIO_WINBOND_W83627HF
select BOARD_ROMSIZE_KB_512
select HAVE_PIRQ_TABLE
select DRIVERS_I2C_W83793
select DRIVERS_GENERIC_IOAPIC
config MAINBOARD_DIR
string
default supermicro/x7db8
config MAINBOARD_PART_NUMBER
string
default "X7DB8 / X7DB8+"
config MMCONF_BASE_ADDRESS
hex
default 0xe0000000
config IRQ_SLOT_COUNT
int
default 48
config MAX_CPUS
int
default 8
endif

2
src/mainboard/supermicro/x7db8/Kconfig.name
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@ -1,2 +0,0 @@
config BOARD_SUPERMICRO_X7DB8
bool "X7DB8 / X7DB8+"

5
src/mainboard/supermicro/x7db8/board_info.txt
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@ -1,5 +0,0 @@
Category: server
Board URL: http://www.supermicro.com/products/motherboard/xeon1333/5000p/x7db8_.cfm
ROM package: PLCC32
ROM protocol: FWH
ROM socketed: y

104
src/mainboard/supermicro/x7db8/cmos.layout
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@ -1,104 +0,0 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2007-2008 coresystems GmbH
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; version 2 of
# the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# -----------------------------------------------------------------
entries
# -----------------------------------------------------------------
# Status Register A
# -----------------------------------------------------------------
# Status Register B
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#390 2 r 0 unused?
# -----------------------------------------------------------------
# coreboot config options: console
#392 3 r 0 unused
395 4 e 6 debug_level
#399 1 r 0 unused
# coreboot config options: cpu
400 1 e 2 hyper_threading
#401 7 r 0 unused
# coreboot config options: southbridge
408 1 e 1 nmi
#409 2 e 7 power_on_after_fail
#411 5 r 0 unused
# coreboot config options: bootloader
416 512 s 0 boot_devices
928 8 h 0 boot_default
936 1 e 8 cmos_defaults_loaded
937 1 e 1 lpt
#938 46 r 0 unused
# coreboot config options: check sums
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 1 Emergency
6 2 Alert
6 3 Critical
6 4 Error
6 5 Warning
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Disable
7 1 Enable
7 2 Keep
8 0 No
8 1 Yes
9 0 Secondary
9 1 Primary
# -----------------------------------------------------------------
checksums
checksum 392 983 984

177
src/mainboard/supermicro/x7db8/devicetree.cb
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2009 coresystems GmbH
## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip northbridge/intel/i5000
device cpu_cluster 0 on
chip cpu/intel/socket_LGA771
device lapic 0 on end
end
end
device domain 0 on
device pci 00.0 on # Host bridge
subsystemid 0x15d9 0x2017
end
device pci 02.0 on # PCI Express x8 Port 2-3
ioapic_irq 8 INTA 0x10
ioapic_irq 8 INTB 0x11
ioapic_irq 8 INTC 0x12
ioapic_irq 8 INTD 0x13
device pci 00.0 on # PCI Express Upstream Port
device pci 00.0 on # PCI Express Downstream Port E1
device pci 00.0 on # 6700PXH PCI Express-to-PCI Bridge A
ioapic_irq 8 INTA 0x11
ioapic_irq 8 INTB 0x10
ioapic_irq 8 INTC 0x11
ioapic_irq 8 INTD 0x10
# PCI slot
device pci 00.2 on # 6700PXH PCI Express-to-PCI Bridge B
# PCI slot
end
device pci 02.0 on # Adaptec U320 #1
ioapic_irq 8 INTA 0x10
end
device pci 02.1 on # Adaptec U320 #2
ioapic_irq 8 INTB 0x11
end
end
end
device pci 00.1 on end
device pci 00.3 on end
end
device pci 03.0 on end
device pci 04.0 on end
device pci 05.0 on end
device pci 06.0 on end
device pci 07.0 on end
device pci 00.3 on # PCI Express to PCI-X Bridge
ioapic_irq 9 INTA 3
ioapic_irq 9 INTB 0
ioapic_irq 9 INTC 1
ioapic_irq 9 INTD 2
# PCI-X Slot
end
end
device pci 03.0 on
ioapic_irq 8 INTA 0x10
end
device pci 04.0 on
ioapic_irq 8 INTA 0x10
end
device pci 05.0 on
ioapic_irq 8 INTA 0x10
end
device pci 06.0 on
ioapic_irq 8 INTA 0x10
end
device pci 07.0 on
ioapic_irq 8 INTA 0x10
end
device pci 10.0 on end # FBD
device pci 10.1 on end # FBD
device pci 10.2 on end # FBD
device pci 11.0 on end # FBD reserved
device pci 13.0 on end # FBD reserved
device pci 15.0 on end # FBD
device pci 16.0 on end # FBD
chip southbridge/intel/i3100
register "pirq_a_d" = "0x0b0b0b0b"
register "pirq_e_h" = "0x80808080"
register "sata_ports_implemented" = "0x3f"
device pci 1c.0 on
ioapic_irq 8 INTA 0x14
ioapic_irq 8 INTB 0x15
ioapic_irq 8 INTC 0x16
ioapic_irq 8 INTD 0x17
end # PCIe bridge
device pci 1d.0 on
ioapic_irq 8 INTA 0x10
end # USB UHCI
device pci 1d.1 on
ioapic_irq 8 INTB 0x11
end # USB UHCI
device pci 1d.2 on
ioapic_irq 8 INTC 0x12
end # USB UHCI
device pci 1d.3 on
ioapic_irq 8 INTD 0x13
end # USB UHCI
device pci 1d.7 on end # USB2 EHCI
device pci 1e.0 on
device pci 01.0 on end
end
device pci 1f.0 on # PCI-LPC bridge
ioapic_irq 8 INTA 0x11
subsystemid 0x15d9 0x2009
chip superio/winbond/w83627hf
device pnp 2e.0 off end # FDC
device pnp 2e.1 on # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Serial Port 1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off end
device pnp 2e.5 on # KBC
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # Game port / MIDI
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 on end # GPIO3
device pnp 2e.a on end # ACPI
device pnp 2e.b off end # HWMON
end
end
device pci 1f.1 off end # IDE
device pci 1f.2 on end # SATA
device pci 1f.3 on
chip drivers/i2c/w83793
register "mfc" = "0x28"
register "fanin" = "0x1f"
register "peci_agent_conf" = "0x33"
register "tcase0" = "0x5e"
register "tcase1" = "0x5e"
register "tcase2" = "0x5e"
register "tcase3" = "0x5e"
register "tr_enable" = "0x01"
register "critical_temperature" = "0x7f"
register "td1_fan_select" = "0x01"
register "td2_fan_select" = "0x01"
register "td3_fan_select" = "0x01"
register "td4_fan_select" = "0x01"
device i2c 0x2f on end
end
end # SMBUS
end
end
end

53
src/mainboard/supermicro/x7db8/irq_tables.c
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/pirq_routing.h>
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x1f << 3) | 0x0, /* Interrupt router dev */
0, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */
0x2670, /* Device */
0, /* Miniport */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0, /* Checksum (has to be set to some value that
* would give 0 after the sum of all bytes
* for this structure (including checksum).
*/
{
/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, (0x1c << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
{0x00, (0x1c << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
{0x00, (0x1c << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0},
{0x00, (0x1c << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0},
{0x00, (0x1d << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
{0x00, (0x1d << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
{0x00, (0x1d << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0},
{0x00, (0x1d << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0},
{0x00, (0x1d << 3) | 0x7, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
{0x00, (0x1f << 3) | 0x1, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
{0x00, (0x1f << 3) | 0x2, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

145
src/mainboard/supermicro/x7db8/romstage.c
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <lib.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <northbridge/intel/i5000/raminit.h>
#include <northbridge/intel/i3100/i3100.h>
#include <southbridge/intel/i3100/i3100.h>
#include <southbridge/intel/i3100/early_smbus.c>
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
#define RCBA_RPC 0x0224 /* 32 bit */
#define RCBA_HPTC 0x3404 /* 32 bit */
#define RCBA_GCS 0x3410 /* 32 bit */
#define RCBA_FD 0x3418 /* 32 bit */
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void early_config(void)
{
u32 gcs, rpc, fd;
/* Enable RCBA */
pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
/* Disable watchdog */
gcs = read32(DEFAULT_RCBA + RCBA_GCS);
gcs |= (1 << 5); /* No reset */
write32(DEFAULT_RCBA + RCBA_GCS, gcs);
/* Configure PCIe port B as 4x */
rpc = read32(DEFAULT_RCBA + RCBA_RPC);
rpc |= (3 << 0);
write32(DEFAULT_RCBA + RCBA_RPC, rpc);
/* Disable Modem, Audio, PCIe ports 2/3/4 */
fd = read32(DEFAULT_RCBA + RCBA_FD);
fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);
write32(DEFAULT_RCBA + RCBA_FD, fd);
/* Enable HPET */
write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));
/* Setup sata mode */
pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40);
}
#define DEFAULT_GPIOBASE 0x1180
static void setup_gpio(void)
{
pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1);
pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4));
outl(0xff0c79cf, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
outl(0xe700ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
outl(0x65b70000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
outl(0x0000718a, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
outl(0x00000106, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
outl(0x00000301, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
outl(0x00030301, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */
}
static void i5000_lpc_config(void)
{
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
}
int mainboard_set_fbd_clock(int speed)
{
switch(speed) {
case 533:
smbus_write_byte(0x6f, 0x80, 0x21);
return 0;
case 667:
smbus_write_byte(0x6f, 0x80, 0x23);
return 0;
default:
printk(BIOS_ERR, "Invalid clock: %dMHz\n", speed);
die("");
return -1;
}
}
void mainboard_romstage_entry(unsigned long bist)
{
if (bist == 0)
enable_lapic();
i5000_lpc_config();
winbond_enable_serial(SERIAL_DEV, 0x3f8);
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
early_config();
setup_gpio();
enable_smbus();
outb(0x07, 0x11b8);
/* These are smbus write captured with serialice. They
seem to setup the clock generator */
smbus_write_byte(0x6f, 0x88, 0x1f);
smbus_write_byte(0x6f, 0x81, 0xff);
smbus_write_byte(0x6f, 0x82, 0xff);
smbus_write_byte(0x6f, 0x80, 0x23);
outb(0x03, 0x11b8);
outb(0x01, 0x11b8);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1);
i5000_fbdimm_init();
smbus_write_byte(0x69, 0x01, 0x01);
}

31
src/northbridge/intel/i5000/Kconfig
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config NORTHBRIDGE_INTEL_I5000
bool
select HAVE_DEBUG_RAM_SETUP
select LATE_CBMEM_INIT
if NORTHBRIDGE_INTEL_I5000
config NORTHBRIDGE_INTEL_I5000_RAM_CHECK
bool
prompt "Run ramcheck after RAM initialization"
config BOOTBLOCK_NORTHBRIDGE_INIT
string
default "northbridge/intel/i5000/bootblock.c"
endif

22
src/northbridge/intel/i5000/Makefile.inc
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#
# This file is part of the coreboot project.
#
# Copyright (C) 2007-2009 coresystems GmbH
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I5000),y)
ramstage-y += northbridge.c
romstage-y += raminit.c
cpu_incs-y += src/northbridge/intel/i5000/halt_second_bsp.S
endif

21
src/northbridge/intel/i5000/bootblock.c
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#include <arch/io.h>
static void bootblock_northbridge_init(void)
{
/*
* The "io" variant of the config access is explicitly used to
* setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
* to true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
* CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
*/
/* setup PCIe MMCONF base address */
pci_io_write_config32(PCI_DEV(0, 16, 0), 0x64,
CONFIG_MMCONF_BASE_ADDRESS >> 16);
}

58
src/northbridge/intel/i5000/halt_second_bsp.S
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@ -1,58 +0,0 @@
/* Save BIST result */
movl %eax, %ebp
/* check if SPAD0 is cleared. If yes, it means this was a hard reset */
movl $0x800080d0, %eax
movw $0xcf8, %dx
outl %eax, %dx
addw $4, %dx
inl %dx, %eax
cmp $0, %eax
je no_reset
/* perform hard reset */
movw $0xcf9, %dx
movb $0x06, %al
outb %al, %dx
loop0: hlt
jmp loop0
no_reset:
/* Read the semaphore register of i5000 (BOFL0).
If it returns zero, it means there was already
another read by another CPU */
movl $0x800080c0, %eax
movw $0xcf8, %dx
outl %eax, %dx
addw $4, %dx
inl %dx, %eax
cmp $0, %eax
jne 1f
/* degrade BSP to AP */
mov $0x1b, %ecx
rdmsr
andl $(~0x100), %eax
wrmsr
cli
loop: hlt
jmp loop
1: /* set magic value for soft reset detection */
movl $0x800080d0, %eax
movw $0xcf8, %dx
outl %eax, %dx
addw $4, %dx
movl $0x12345678, %eax
outl %eax, %dx
/* Restore BIST */
mov %ebp, %eax

177
src/northbridge/intel/i5000/northbridge.c
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <arch/io.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <stdlib.h>
#include <string.h>
#include <cpu/cpu.h>
#include <arch/acpi.h>
#include <cbmem.h>
static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static void mc_read_resources(device_t dev)
{
struct resource *resource;
uint32_t hecbase, amsize, tolm;
uint64_t ambase, memsize;
int idx = 0;
device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0));
device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1));
pci_dev_read_resources(dev);
tolm = pci_read_config16(dev_find_slot(0, PCI_DEVFN(16, 1)), 0x6c) << 16;
hecbase = pci_read_config16(dev16_0, 0x64) >> 12;
hecbase &= 0xffff;
ambase = ((u64)pci_read_config32(dev16_0, 0x48) |
(u64)pci_read_config32(dev16_0, 0x4c) << 32);
amsize = pci_read_config32(dev16_0, 0x50);
ambase &= 0x000000ffffff0000;
printk(BIOS_DEBUG, "TOLM: 0x%08x AMBASE: 0x%016llx\n", tolm, ambase);
/* Report the memory regions */
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, ((tolm >> 10) - 768));
memsize = MAX(pci_read_config16(dev16_1, 0x80) & ~3,
pci_read_config16(dev16_1, 0x84) & ~3);
memsize = MAX(memsize, pci_read_config16(dev16_1, 0x88) & ~3);
memsize <<= 24;
printk(BIOS_INFO, "MEMSIZE: %08llx\n", memsize);
if (memsize > 0xd0000000) {
memsize -= 0xd0000000;
printk(BIOS_INFO, "high memory: %lldMB\n", memsize / 1048576);
ram_resource(dev, idx++, 4096 * 1024, memsize / 1024);
}
if (hecbase) {
printk(BIOS_DEBUG, "Adding PCIe config bar at 0x%016llx\n", (u64)hecbase << 28);
resource = new_resource(dev, idx++);
resource->base = (resource_t)(uint64_t)hecbase << 28;
resource->size = (resource_t)256 * 1024 * 1024;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
resource = new_resource(dev, idx++);
resource->base = (resource_t)(uint64_t)0xffe00000;
resource->size = (resource_t)0x200000;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
if (ambase && amsize) {
resource = new_resource(dev, idx++);
resource->base = (resource_t)ambase;
resource->size = (resource_t)amsize;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
/* add resource for 0xfe6xxxxx range. This range is used by i5000 for
various fixed address registers (BOFL, SPAD, SPADS */
resource = new_resource(dev, idx++);
resource->base = (resource_t)0xfe600000;
resource->size = (resource_t)0x00100000;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
set_late_cbmem_top(tolm);
}
static struct pci_operations intel_pci_ops = {
.set_subsystem = intel_set_subsystem,
};
static struct device_operations mc_ops = {
.read_resources = mc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.scan_bus = 0,
.ops_pci = &intel_pci_ops,
};
static const unsigned short nb_ids[] = {
0x25c0, /* 5000X */
0x25d0, /* 5000Z */
0x25d4, /* 5000V */
0x25d8, /* 5000P */
0};
static const struct pci_driver mc_driver __pci_driver = {
.ops = &mc_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = nb_ids,
};
static void cpu_bus_init(device_t dev)
{
initialize_cpus(dev->link_list);
}
static struct device_operations cpu_bus_ops = {
.read_resources = DEVICE_NOOP,
.set_resources = DEVICE_NOOP,
.enable_resources = DEVICE_NOOP,
.init = cpu_bus_init,
.scan_bus = 0,
};
static void pci_domain_set_resources(device_t dev)
{
assign_resources(dev->link_list);
}
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
};
static void enable_dev(device_t dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
}
}
struct chip_operations northbridge_intel_i5000_ops = {
CHIP_NAME("Intel i5000 Northbridge")
.enable_dev = enable_dev,
};

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src/northbridge/intel/i5000/raminit.c
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src/northbridge/intel/i5000/raminit.h
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef NORTHBRIDGE_I5000_RAMINIT_H
#define NORTHBRIDGE_I5000_RAMINIT_H
#include <types.h>
#include <arch/io.h>
#define I5000_MAX_BRANCH 2
#define I5000_MAX_CHANNEL 2
#define I5000_MAX_DIMM_PER_CHANNEL 4
#define I5000_MAX_DIMMS (I5000_MAX_BRANCH * I5000_MAX_CHANNEL * I5000_MAX_DIMM_PER_CHANNEL)
#define I5000_FBDRST 0x53
#define I5000_SPD_BUSY (1 << 12)
#define I5000_SPD_SBE (1 << 13)
#define I5000_SPD_WOD (1 << 14)
#define I5000_SPD_RDO (1 << 15)
#define I5000_SPD0 0x74
#define I5000_SPD1 0x76
#define I5000_SPDCMD0 0x78
#define I5000_SPDCMD1 0x7c
#define I5000_FBDHPC 0x4f
#define I5000_FBDST 0x4b
#define I5000_FBDHPC_STATE_RESET 0x00
#define I5000_FBDHPC_STATE_INIT 0x10
#define I5000_FBDHPC_STATE_READY 0x20
#define I5000_FBDHPC_STATE_ACTIVE 0x30
#define I5000_FBDISTS0 0x58
#define I5000_FBDISTS1 0x5a
#define I5000_FBDLVL0 0x44
#define I5000_FBDLVL1 0x45
#define I5000_FBDICMD0 0x46
#define I5000_FBDICMD1 0x47
#define I5000_FBDICMD_IDLE 0x00
#define I5000_FBDICMD_TS0 0x80
#define I5000_FBDICMD_TS1 0x90
#define I5000_FBDICMD_TS2 0xa0
#define I5000_FBDICMD_TS3 0xb0
#define I5000_FBDICMD_TS2_MERGE 0xd0
#define I5000_FBDICMD_TS2_NOMERGE 0xe0
#define I5000_FBDICMD_ALL_ONES 0xf0
#define I5000_AMBPRESENT0 0x64
#define I5000_AMBPRESENT1 0x66
#define I5000_FBDSBTXCFG0 0xc0
#define I5000_FBDSBTXCFG1 0xc1
#define I5000_PROCENABLE 0xf0
#define I5000_FBD0IBPORTCTL 0x180
#define I5000_FBD0IBTXPAT2EN 0x1a8
#define I5000_FBD0IBRXPAT2EN 0x1ac
#define I5000_FBD0IBTXMSK 0x18c
#define I5000_FBD0IBRXMSK 0x190
#define I5000_FBDPLLCTRL 0x1c0
/* dev 16, function 1 registers */
#define I5000_MC 0x40
#define I5000_DRTA 0x48
#define I5000_DRTB 0x4c
#define I5000_ERRPERR 0x50
#define I5000_MCA 0x58
#define I5000_TOLM 0x6c
#define I5000_MIR0 0x80
#define I5000_MIR1 0x84
#define I5000_MIR2 0x88
#define I5000_AMIR0 0x8c
#define I5000_AMIR1 0x90
#define I5000_AMIR2 0x94
#define I5000_FERR_FAT_FBD 0x98
#define I5000_NERR_FAT_FBD 0x9c
#define I5000_FERR_NF_FBD 0xa0
#define I5000_NERR_NF_FBD 0xa4
#define I5000_EMASK_FBD 0xa8
#define I5000_ERR0_FBD 0xac
#define I5000_ERR1_FBD 0xb0
#define I5000_ERR2_FBD 0xb4
#define I5000_MCERR_FBD 0xb8
#define I5000_NRECMEMA 0xbe
#define I5000_NRECMEMB 0xc0
#define I5000_NRECFGLOG 0xc4
#define I5000_NRECMEMA 0xbe
#define I5000_NRECFBDA 0xc8
#define I5000_NRECFBDB 0xcc
#define I5000_NRECFBDC 0xd0
#define I5000_NRECFBDD 0xd4
#define I5000_NRECFBDE 0xd8
#define I5000_REDMEMB 0x7c
#define I5000_RECMEMA 0xe2
#define I5000_RECMEMB 0xe4
#define I5000_RECFGLOG 0xe8
#define I5000_RECFBDA 0xec
#define I5000_RECFBDB 0xf0
#define I5000_RECFBDC 0xf4
#define I5000_RECFBDD 0xf8
#define I5000_RECFBDE 0xfc
#define I5000_FBDTOHOSTGRCFG0 0x160
#define I5000_FBDTOHOSTGRCFG1 0x164
#define I5000_HOSTTOFBDGRCFG 0x168
#define I5000_GRFBDLVLDCFG 0x16c
#define I5000_GRHOSTFULLCFG 0x16d
#define I5000_GRBUBBLECFG 0x16e
#define I5000_GRFBDTOHOSTDBLCFG 0x16f
/* dev 16, function 2 registers */
#define I5000_FERR_GLOBAL 0x40
#define I5000_NERR_GLOBAL 0x44
/* dev 21, function 0 registers */
#define I5000_MTR0 0x80
#define I5000_MTR1 0x84
#define I5000_MTR2 0x88
#define I5000_MTR3 0x8c
#define I5000_DMIR0 0x90
#define I5000_DMIR1 0x94
#define I5000_DMIR2 0x98
#define I5000_DMIR3 0x9c
#define I5000_DMIR4 0xa0
#define DEFAULT_AMBASE ((u8 *)0xfe000000)
/* AMB function 1 registers */
#define AMB_FBDSBCFGNXT 0x54
#define AMB_FBDLOCKTO 0x68
#define AMB_EMASK 0x8c
#define AMB_FERR 0x90
#define AMB_NERR 0x94
#define AMB_CMD2DATANXT 0xe8
/* AMB function 3 registers */
#define AMB_DAREFTC 0x70
#define AMB_DSREFTC 0x74
#define AMB_DRT 0x78
#define AMB_DRC 0x7c
#define AMB_MBCSR 0x40
#define AMB_MBADDR 0x44
#define AMB_MBLFSRSED 0xa4
/* AMB function 4 registers */
#define AMB_DCALCSR 0x40
#define AMB_DCALADDR 0x44
#define AMB_DCALCSR_START (1 << 31)
#define AMB_DCALCSR_OPCODE_NOP 0x00
#define AMB_DCALCSR_OPCODE_REFRESH 0x01
#define AMB_DCALCSR_OPCODE_PRECHARGE 0x02
#define AMB_DCALCSR_OPCODE_MRS_EMRS 0x03
#define AMB_DCALCSR_OPCODE_DQS_DELAY_CAL 0x05
#define AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL 0x0c
#define AMB_DCALCSR_OPCODE_SELF_REFRESH_ENTRY 0x0d
#define AMB_DDR2ODTC 0xfc
#define FBDIMM_SPD_SDRAM_ADDRESSING 0x04
#define FBDIMM_SPD_MODULE_ORGANIZATION 0x07
#define FBDIMM_SPD_FTB 0x08
#define FBDIMM_SPD_MTB_DIVIDEND 0x09
#define FBDIMM_SPD_MTB_DIVISOR 0x0a
#define FBDIMM_SPD_MIN_TCK 0x0b
#define FBDIMM_SPD_CAS_LATENCIES 0x0d
#define FBDIMM_SPD_CAS_MIN_LATENCY 0x0e
#define FBDIMM_SPD_T_WR 0x10
#define FBDIMM_SPD_T_RCD 0x13
#define FBDIMM_SPD_T_RRD 0x14
#define FBDIMM_SPD_T_RP 0x15
#define FBDIMM_SPD_T_RAS_RC_MSB 0x16
#define FBDIMM_SPD_T_RAS 0x17
#define FBDIMM_SPD_T_RC 0x18
#define FBDIMM_SPD_T_RFC 0x19
#define FBDIMM_SPD_T_WTR 0x1b
#define FBDIMM_SPD_T_RTP 0x1c
#define FBDIMM_SPD_BURST_LENGTHS_SUPPORTED 0x1d
#define FBDIMM_SPD_ODT 0x4f
#define FBDIMM_SPD_T_REFI 0x20
#define FBDIMM_SPD_T_BB 0x83
#define FBDIMM_SPD_CMD2DATA_800 0x54
#define FBDIMM_SPD_CMD2DATA_667 0x55
#define FBDIMM_SPD_CMD2DATA_533 0x56
void i5000_fbdimm_init(void);
#define I5000_BURST4 0x01
#define I5000_BURST8 0x02
#define I5000_BURST_CHOP 0x80
#define I5000_ODT_50 4
#define I5000_ODT_75 2
#define I5000_ODT_150 1
enum ddr_speeds {
DDR_533MHZ,
DDR_667MHZ,
DDR_MAX,
};
struct i5000_fbdimm {
struct i5000_fbd_branch *branch;
struct i5000_fbd_channel *channel;
struct i5000_fbd_setup *setup;
enum ddr_speeds speed;
int num;
int present:1;
u32 ambase;
/* SPD data */
u8 amb_personality_bytes[14];
u8 banks;
u8 rows;
u8 columns;
u8 ranks;
u8 odt;
u8 sdram_width;
u8 mtb_divisor;
u8 mtb_dividend;
u8 t_ck_min;
u8 min_cas_latency;
u8 t_rrd;
u16 t_rfc;
u8 t_wtr;
u8 t_refi;
u8 cmd2datanxt[DDR_MAX];
u16 vendor;
u16 device;
/* memory rank size in MB */
int ranksize;
};
struct i5000_fbd_channel {
struct i5000_fbdimm dimm[I5000_MAX_DIMM_PER_CHANNEL];
struct i5000_fbd_branch *branch;
struct i5000_fbd_setup *setup;
int num;
int used;
int highest_amb;
int columns;
int rows;
int ranks;
int banks;
int width;
/* memory size in MB on this channel */
int totalmem;
};
struct i5000_fbd_branch {
struct i5000_fbd_channel channel[I5000_MAX_CHANNEL];
struct i5000_fbd_setup *setup;
pci_devfn_t branchdev;
int num;
int used;
/* memory size in MB on this branch */
int totalmem;
};
enum odt {
ODT_150OHM=1,
ODT_50OHM=4,
ODT_75OHM=2,
};
enum bl {
BL_BL4=1,
BL_BL8=2,
};
struct i5000_fbd_setup {
struct i5000_fbd_branch branch[I5000_MAX_BRANCH];
struct i5000_fbdimm *dimms[I5000_MAX_DIMMS];
enum bl bl;
enum ddr_speeds ddr_speed;
int single_channel:1;
u32 tolm;
/* global SDRAM timing parameters */
u8 t_al;
u8 t_cl;
u8 t_ras;
u8 t_wrc;
u8 t_rc;
u8 t_rfc;
u8 t_rrd;
u8 t_ref;
u8 t_w2rdr;
u8 t_r2w;
u8 t_w2r;
u8 t_r2r;
u8 t_w2w;
u8 t_wtr;
u8 t_rcd;
u8 t_rp;
u8 t_wr;
u8 t_rtp;
/* memory size in MB */
int totalmem;
};
int mainboard_set_fbd_clock(int);
#define AMB_ADDR(base, fn, reg) (base | ((fn & 7) << 8) | ((reg & 0xff)))
#endif