intel: Use MSR_EBC_FREQUENCY_ID instead of 0x2c

Change-Id: Ib1b761fc417f1bb000f408d3bed5e8666963f51d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/22603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Martin Roth <martinroth@google.com>

src/cpu/x86/lapic/apic_timer.c

@@ -48,6 +48,7 @@ static int set_timer_fsb(void)
 	int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
 	int core2_fsb[8] = { 266, 133, 200, 166, 333, 100, -1, -1 };
 	int f2x_fsb[8] = { 100, 133, 200, 166, -1, -1, -1, -1 };
+	msr_t msr;
 
 	get_fms(&c, cpuid_eax(1));
 	switch (c.x86) {
@@ -74,16 +75,17 @@ static int set_timer_fsb(void)
 			return 0;
 		}
 	case 0xf: /* Netburst */
+		msr = rdmsr(MSR_EBC_FREQUENCY_ID);
 		switch (c.x86_model) {
 		case 0x2:
 			car_set_var(g_timer_fsb,
-				f2x_fsb[(rdmsr(0x2c).lo >> 16) & 7]);
+				f2x_fsb[(msr.lo >> 16) & 7]);
 			return 0;
 		case 0x3:
 		case 0x4:
 		case 0x6:
 			car_set_var(g_timer_fsb,
-				core2_fsb[(rdmsr(0x2c).lo >> 16) & 7]);
+				core2_fsb[(msr.lo >> 16) & 7]);
 			return 0;
 		}  /* default: fallthrough */
 	default:

src/include/cpu/intel/speedstep.h

@@ -40,6 +40,7 @@
 #define IA32_PERF_CTL     0x199
 #define MSR_THERM2_CTL    0x19D
 #define IA32_MISC_ENABLES 0x1A0
+#define MSR_EBC_FREQUENCY_ID	0x2c
 #define MSR_FSB_FREQ		0xcd
 #define MSR_FSB_CLOCK_VCC	0xce
 #define MSR_PMG_CST_CONFIG_CONTROL	0xe2

src/mainboard/asus/p5gc-mx/romstage.c

@@ -94,7 +94,7 @@ static u8 msr_get_fsb(void)
 
 	/* Netburst */
 	if (((eax >> 8) & 0xf) == 0xf) {
-		msr = rdmsr(0x2c);
+		msr = rdmsr(MSR_EBC_FREQUENCY_ID);
 		fsbcfg = (msr.lo >> 16) & 0x7;
 	} else { /* Intel Core 2 */
 		msr = rdmsr(MSR_FSB_FREQ);