intel/nehalem,sandybridge: Move stage_cache support function
Let garbage-collection take care of stage_cache_external_region() if it is no needed and move implementation to a suitable file already building for needed stages. Remove aliasing CONFIG_RESERVED_SMM_SIZE as RESERVED_SMM_SIZE and (unused) aliasing of CONFIG_IED_REGION_SIZE as IED_SIZE. Change-Id: Idf00ba3180d8c3bc974dd3c5ca5f98a6c08bf34d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34672 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
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f6c20681d1
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@ -19,10 +19,6 @@ ramstage-y += acpi.c
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smm-y += finalize.c
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smm-y += finalize.c
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romstage-y += stage_cache.c
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ramstage-y += stage_cache.c
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postcar-y += stage_cache.c
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cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*)
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cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*)
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cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
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cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
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@ -80,16 +80,9 @@ void set_power_limits(u8 power_limit_1_time);
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int cpu_config_tdp_levels(void);
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int cpu_config_tdp_levels(void);
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#endif
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#endif
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/*
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* Region of SMM space is reserved for multipurpose use. It falls below
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* the IED region and above the SMM handler.
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*/
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#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE
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#define RESERVED_SMM_OFFSET (CONFIG_SMM_TSEG_SIZE - RESERVED_SMM_SIZE)
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/* Sanity check config options. */
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/* Sanity check config options. */
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#if (CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE)
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#if (CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE)
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# error "CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE"
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# error "CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE"
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#endif
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#endif
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#if (CONFIG_SMM_TSEG_SIZE < 0x800000)
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#if (CONFIG_SMM_TSEG_SIZE < 0x800000)
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# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
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# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
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@ -1,30 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cbmem.h>
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#include <stage_cache.h>
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#include <cpu/intel/smm/gen1/smi.h>
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#include "model_2065x.h"
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void stage_cache_external_region(void **base, size_t *size)
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{
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/*
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* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
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* The top of RAM is defined to be the TSEG base address.
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*/
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*size = RESERVED_SMM_SIZE;
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*base = (void *)((uintptr_t)northbridge_get_tseg_base()
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+ RESERVED_SMM_OFFSET);
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}
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@ -24,10 +24,6 @@ smm-y += tsc_freq.c
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smm-y += finalize.c
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smm-y += finalize.c
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romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
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postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
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ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
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cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*)
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cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*)
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cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*)
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cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*)
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@ -81,17 +81,9 @@
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#define PSS_LATENCY_TRANSITION 10
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#define PSS_LATENCY_TRANSITION 10
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#define PSS_LATENCY_BUSMASTER 10
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#define PSS_LATENCY_BUSMASTER 10
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/*
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* Region of SMM space is reserved for multipurpose use. It falls below
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* the IED region and above the SMM handler.
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*/
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#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE
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#define RESERVED_SMM_OFFSET \
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(CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE)
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/* Sanity check config options. */
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/* Sanity check config options. */
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#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE))
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#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE))
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# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)"
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# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)"
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#endif
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#endif
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#if (CONFIG_SMM_TSEG_SIZE < 0x800000)
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#if (CONFIG_SMM_TSEG_SIZE < 0x800000)
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# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
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# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
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@ -1,28 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cbmem.h>
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#include <stage_cache.h>
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#include "model_206ax.h"
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void stage_cache_external_region(void **base, size_t *size)
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{
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/*
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* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
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* The top of RAM is defined to be the TSEG base address.
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*/
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*size = RESERVED_SMM_SIZE;
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*base = (void *)((uintptr_t)cbmem_top() + RESERVED_SMM_OFFSET);
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}
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@ -122,9 +122,6 @@ typedef struct {
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#define IVB_STEP_K0 (BASE_REV_IVB + 5)
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#define IVB_STEP_K0 (BASE_REV_IVB + 5)
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#define IVB_STEP_D0 (BASE_REV_IVB + 6)
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#define IVB_STEP_D0 (BASE_REV_IVB + 6)
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/* Intel Enhanced Debug region must be 4MB */
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#define IED_SIZE 0x400000
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/* Northbridge BARs */
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/* Northbridge BARs */
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#ifndef __ACPI__
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#ifndef __ACPI__
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#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */
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#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */
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@ -171,11 +171,6 @@ static void mc_read_resources(struct device *dev)
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add_fixed_resources(dev, 10);
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add_fixed_resources(dev, 10);
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}
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}
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u32 northbridge_get_tseg_size(void)
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{
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return CONFIG_SMM_TSEG_SIZE;
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}
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static void mc_set_resources(struct device *dev)
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static void mc_set_resources(struct device *dev)
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{
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{
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/* And call the normal set_resources */
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/* And call the normal set_resources */
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@ -23,6 +23,7 @@
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#include <cpu/intel/romstage.h>
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#include <cpu/intel/romstage.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/mtrr.h>
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#include <program_loading.h>
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#include <program_loading.h>
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#include <stage_cache.h>
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#include <cpu/intel/smm/gen1/smi.h>
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#include <cpu/intel/smm/gen1/smi.h>
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#include "nehalem.h"
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#include "nehalem.h"
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@ -38,11 +39,25 @@ u32 northbridge_get_tseg_base(void)
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return (u32)smm_region_start();
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return (u32)smm_region_start();
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}
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}
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u32 northbridge_get_tseg_size(void)
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{
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return CONFIG_SMM_TSEG_SIZE;
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}
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void *cbmem_top(void)
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void *cbmem_top(void)
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{
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{
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return (void *) smm_region_start();
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return (void *) smm_region_start();
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}
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}
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void stage_cache_external_region(void **base, size_t *size)
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{
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/* The stage cache lives at the end of TSEG region.
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* The top of RAM is defined to be the TSEG base address. */
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*size = CONFIG_SMM_RESERVED_SIZE;
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*base = (void *)((uintptr_t)northbridge_get_tseg_base() +
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northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
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}
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/* platform_enter_postcar() determines the stack to use after
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/* platform_enter_postcar() determines the stack to use after
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* cache-as-ram is torn down as well as the MTRR settings to use,
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* cache-as-ram is torn down as well as the MTRR settings to use,
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* and continues execution in postcar stage. */
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* and continues execution in postcar stage. */
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@ -444,28 +444,6 @@ static void northbridge_init(struct device *dev)
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MCHBAR32(0x5500) = 0x00100001;
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MCHBAR32(0x5500) = 0x00100001;
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}
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}
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static u32 northbridge_get_base_reg(struct device *dev, int reg)
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{
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u32 value;
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value = pci_read_config32(dev, reg);
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/* Base registers are at 1MiB granularity. */
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value &= ~((1 << 20) - 1);
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return value;
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}
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u32 northbridge_get_tseg_base(void)
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{
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struct device *dev = pcidev_on_root(0, 0);
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return northbridge_get_base_reg(dev, TSEG);
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}
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u32 northbridge_get_tseg_size(void)
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{
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return CONFIG_SMM_TSEG_SIZE;
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}
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void northbridge_write_smram(u8 smram)
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void northbridge_write_smram(u8 smram)
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{
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{
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pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram);
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pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram);
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@ -20,17 +20,12 @@
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#include <cbmem.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <cpu/intel/romstage.h>
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#include <cpu/intel/romstage.h>
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#include <cpu/intel/smm/gen1/smi.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/mtrr.h>
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#include <program_loading.h>
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#include <program_loading.h>
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#include <stage_cache.h>
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#include "sandybridge.h"
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#include "sandybridge.h"
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#if (CONFIG_SMM_TSEG_SIZE < 0x800000)
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# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
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#endif
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#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0)
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# error "CONFIG_SMM_TSEG_SIZE is not a power of 2"
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#endif
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static uintptr_t smm_region_start(void)
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static uintptr_t smm_region_start(void)
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{
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{
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/* Base of TSEG is top of usable DRAM */
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/* Base of TSEG is top of usable DRAM */
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return (void *) smm_region_start();
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return (void *) smm_region_start();
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}
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}
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u32 northbridge_get_tseg_base(void)
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{
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return ALIGN_DOWN(smm_region_start(), 1*MiB);
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}
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u32 northbridge_get_tseg_size(void)
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{
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return CONFIG_SMM_TSEG_SIZE;
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}
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void stage_cache_external_region(void **base, size_t *size)
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{
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/* The stage cache lives at the end of TSEG region.
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* The top of RAM is defined to be the TSEG base address. */
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*size = CONFIG_SMM_RESERVED_SIZE;
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*base = (void *)((uintptr_t)northbridge_get_tseg_base() + northbridge_get_tseg_size()
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- CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE);
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}
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/* platform_enter_postcar() determines the stack to use after
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/* platform_enter_postcar() determines the stack to use after
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* cache-as-ram is torn down as well as the MTRR settings to use,
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* cache-as-ram is torn down as well as the MTRR settings to use,
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* and continues execution in postcar stage. */
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* and continues execution in postcar stage. */
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#define IVB_STEP_K0 (BASE_REV_IVB + 5)
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#define IVB_STEP_K0 (BASE_REV_IVB + 5)
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#define IVB_STEP_D0 (BASE_REV_IVB + 6)
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#define IVB_STEP_D0 (BASE_REV_IVB + 6)
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/* Intel Enhanced Debug region must be 4MB */
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#define IED_SIZE CONFIG_IED_REGION_SIZE
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/* Northbridge BARs */
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/* Northbridge BARs */
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#ifndef __ACPI__
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#ifndef __ACPI__
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#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */
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#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */
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