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intel/nehalem,sandybridge: Move stage_cache support function 

Let garbage-collection take care of stage_cache_external_region()
if it is no needed and move implementation to a suitable file already
building for needed stages.

Remove aliasing CONFIG_RESERVED_SMM_SIZE as RESERVED_SMM_SIZE and
(unused) aliasing of CONFIG_IED_REGION_SIZE as IED_SIZE.

Change-Id: Idf00ba3180d8c3bc974dd3c5ca5f98a6c08bf34d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34672
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-08-02 06:14:50 +03:00
parent 0b7cc927b6
commit f6c20681d1
12 changed files with 40 additions and 126 deletions
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4
src/cpu/intel/model_2065x/Makefile.inc
View File

@ -19,10 +19,6 @@ ramstage-y += acpi.c
smm-y += finalize.c
romstage-y += stage_cache.c
ramstage-y += stage_cache.c
postcar-y += stage_cache.c
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*)
cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S

11
src/cpu/intel/model_2065x/model_2065x.h
View File

@ -80,16 +80,9 @@ void set_power_limits(u8 power_limit_1_time);
int cpu_config_tdp_levels(void);
#endif
/*
* Region of SMM space is reserved for multipurpose use. It falls below
* the IED region and above the SMM handler.
*/
#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE
#define RESERVED_SMM_OFFSET (CONFIG_SMM_TSEG_SIZE - RESERVED_SMM_SIZE)
/* Sanity check config options. */
#if (CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE)
# error "CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE"
#if (CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE)
# error "CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE"
#endif
#if (CONFIG_SMM_TSEG_SIZE < 0x800000)
# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"

30
src/cpu/intel/model_2065x/stage_cache.c
View File

@ -1,30 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cbmem.h>
#include <stage_cache.h>
#include <cpu/intel/smm/gen1/smi.h>
#include "model_2065x.h"
void stage_cache_external_region(void **base, size_t *size)
{
/*
* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
* The top of RAM is defined to be the TSEG base address.
*/
*size = RESERVED_SMM_SIZE;
*base = (void *)((uintptr_t)northbridge_get_tseg_base()
+ RESERVED_SMM_OFFSET);
}

4
src/cpu/intel/model_206ax/Makefile.inc
View File

@ -24,10 +24,6 @@ smm-y += tsc_freq.c
smm-y += finalize.c
romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*)
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*)

12
src/cpu/intel/model_206ax/model_206ax.h
View File

@ -81,17 +81,9 @@
#define PSS_LATENCY_TRANSITION 10
#define PSS_LATENCY_BUSMASTER 10
/*
* Region of SMM space is reserved for multipurpose use. It falls below
* the IED region and above the SMM handler.
*/
#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE
#define RESERVED_SMM_OFFSET \
(CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE)
/* Sanity check config options. */
#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE))
# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)"
#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE))
# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)"
#endif
#if (CONFIG_SMM_TSEG_SIZE < 0x800000)
# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"

28
src/cpu/intel/model_206ax/stage_cache.c
View File

@ -1,28 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cbmem.h>
#include <stage_cache.h>
#include "model_206ax.h"
void stage_cache_external_region(void **base, size_t *size)
{
/*
* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
* The top of RAM is defined to be the TSEG base address.
*/
*size = RESERVED_SMM_SIZE;
*base = (void *)((uintptr_t)cbmem_top() + RESERVED_SMM_OFFSET);
}

3
src/northbridge/intel/nehalem/nehalem.h
View File

@ -122,9 +122,6 @@ typedef struct {
#define IVB_STEP_K0 (BASE_REV_IVB + 5)
#define IVB_STEP_D0 (BASE_REV_IVB + 6)
/* Intel Enhanced Debug region must be 4MB */
#define IED_SIZE 0x400000
/* Northbridge BARs */
#ifndef __ACPI__
#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */

5
src/northbridge/intel/nehalem/northbridge.c
View File

@ -171,11 +171,6 @@ static void mc_read_resources(struct device *dev)
add_fixed_resources(dev, 10);
}
u32 northbridge_get_tseg_size(void)
{
return CONFIG_SMM_TSEG_SIZE;
}
static void mc_set_resources(struct device *dev)
{
/* And call the normal set_resources */

15
src/northbridge/intel/nehalem/ram_calc.c
View File

@ -23,6 +23,7 @@
#include <cpu/intel/romstage.h>
#include <cpu/x86/mtrr.h>
#include <program_loading.h>
#include <stage_cache.h>
#include <cpu/intel/smm/gen1/smi.h>
#include "nehalem.h"
@ -38,11 +39,25 @@ u32 northbridge_get_tseg_base(void)
return (u32)smm_region_start();
}
u32 northbridge_get_tseg_size(void)
{
return CONFIG_SMM_TSEG_SIZE;
}
void *cbmem_top(void)
{
return (void *) smm_region_start();
}
void stage_cache_external_region(void **base, size_t *size)
{
/* The stage cache lives at the end of TSEG region.
* The top of RAM is defined to be the TSEG base address. */
*size = CONFIG_SMM_RESERVED_SIZE;
*base = (void *)((uintptr_t)northbridge_get_tseg_base() +
northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
}
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */

22
src/northbridge/intel/sandybridge/northbridge.c
View File

@ -444,28 +444,6 @@ static void northbridge_init(struct device *dev)
MCHBAR32(0x5500) = 0x00100001;
}
static u32 northbridge_get_base_reg(struct device *dev, int reg)
{
u32 value;
value = pci_read_config32(dev, reg);
/* Base registers are at 1MiB granularity. */
value &= ~((1 << 20) - 1);
return value;
}
u32 northbridge_get_tseg_base(void)
{
struct device *dev = pcidev_on_root(0, 0);
return northbridge_get_base_reg(dev, TSEG);
}
u32 northbridge_get_tseg_size(void)
{
return CONFIG_SMM_TSEG_SIZE;
}
void northbridge_write_smram(u8 smram)
{
pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram);

28
src/northbridge/intel/sandybridge/ram_calc.c
View File

@ -20,17 +20,12 @@
#include <cbmem.h>
#include <console/console.h>
#include <cpu/intel/romstage.h>
#include <cpu/intel/smm/gen1/smi.h>
#include <cpu/x86/mtrr.h>
#include <program_loading.h>
#include <stage_cache.h>
#include "sandybridge.h"
#if (CONFIG_SMM_TSEG_SIZE < 0x800000)
# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
#endif
#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0)
# error "CONFIG_SMM_TSEG_SIZE is not a power of 2"
#endif
static uintptr_t smm_region_start(void)
{
/* Base of TSEG is top of usable DRAM */
@ -43,6 +38,25 @@ void *cbmem_top(void)
return (void *) smm_region_start();
}
u32 northbridge_get_tseg_base(void)
{
return ALIGN_DOWN(smm_region_start(), 1*MiB);
}
u32 northbridge_get_tseg_size(void)
{
return CONFIG_SMM_TSEG_SIZE;
}
void stage_cache_external_region(void **base, size_t *size)
{
/* The stage cache lives at the end of TSEG region.
* The top of RAM is defined to be the TSEG base address. */
*size = CONFIG_SMM_RESERVED_SIZE;
*base = (void *)((uintptr_t)northbridge_get_tseg_base() + northbridge_get_tseg_size()
- CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE);
}
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */

4
src/northbridge/intel/sandybridge/sandybridge.h
View File

@ -34,10 +34,6 @@
#define IVB_STEP_K0 (BASE_REV_IVB + 5)
#define IVB_STEP_D0 (BASE_REV_IVB + 6)
/* Intel Enhanced Debug region must be 4MB */
#define IED_SIZE CONFIG_IED_REGION_SIZE
/* Northbridge BARs */
#ifndef __ACPI__
#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */