soc/intel/baytrail: Use postcar_frame functions to set up frame
Change-Id: I77e375a2ff2fbf1be4ded922195b80b49ffa4cc5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29929 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -241,76 +241,31 @@ static inline uint32_t *stack_push(u32 *stack, u32 value)
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return stack;
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}
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#define ROMSTAGE_RAM_STACK_SIZE 0x5000
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/* setup_stack_and_mtrrs() determines the stack to use after
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* cache-as-ram is torn down as well as the MTRR settings to use. */
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static void *setup_stack_and_mtrrs(void)
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{
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int num_mtrrs;
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uint32_t *slot;
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uint32_t mtrr_mask_upper;
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uint32_t top_of_ram;
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/* Top of stack needs to be aligned to a 4-byte boundary. */
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slot = (void *)romstage_ram_stack_top();
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num_mtrrs = 0;
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/* The upper bits of the MTRR mask need to set according to the number
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* of physical address bits. */
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mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
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/* The order for each MTRR is value then base with upper 32-bits of
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* each value coming before the lower 32-bits. The reasoning for
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* this ordering is to create a stack layout like the following:
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* +0: Number of MTRRs
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* +4: MTRR base 0 31:0
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* +8: MTRR base 0 63:32
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* +12: MTRR mask 0 31:0
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* +16: MTRR mask 0 63:32
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* +20: MTRR base 1 31:0
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* +24: MTRR base 1 63:32
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* +28: MTRR mask 1 31:0
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* +32: MTRR mask 1 63:32
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*/
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struct postcar_frame pcf;
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uintptr_t top_of_ram;
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if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
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die("Unable to initialize postcar frame.\n");
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/* Cache the ROM as WP just below 4GiB. */
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slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
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slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);
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slot = stack_push(slot, 0); /* upper base */
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slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
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num_mtrrs++;
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postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
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MTRR_TYPE_WRPROT);
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
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slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
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slot = stack_push(slot, 0); /* upper base */
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slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
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num_mtrrs++;
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postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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top_of_ram = (uint32_t)cbmem_top();
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/* Cache 8MiB below the top of ram. The top of RAM under 4GiB is the
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* start of the TSEG region. It is required to be 8MiB aligned. Set
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* this area as cacheable so it can be used later for ramstage before
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* setting up the entire RAM as cacheable. */
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slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
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slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
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slot = stack_push(slot, 0); /* upper base */
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slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
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num_mtrrs++;
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/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
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* above top of the ram. This satisfies MTRR alignment requirement
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* with different TSEG size configurations.
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*/
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top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
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postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB,
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MTRR_TYPE_WRBACK);
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/* Cache 8MiB at the top of ram. Top of RAM is where the TSEG
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* region resides. However, it is not restricted to SMM mode until
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* SMM has been relocated. By setting the region to cacheable it
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* provides faster access when relocating the SMM handler as well
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* as using the TSEG region for other purposes. */
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slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
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slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
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slot = stack_push(slot, 0); /* upper base */
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slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);
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num_mtrrs++;
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/* Save the number of MTRRs to setup. Return the stack location
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* pointing to the number of MTRRs. */
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slot = stack_push(slot, num_mtrrs);
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return slot;
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return postcar_commit_mtrrs(&pcf);
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}
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