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imgtec/pistachio: increase CBFS cache 

Increase CBFS cache size to allow for a bigger payload.

Change-Id: I47404ba9bbe95f6610189b971504019c0a1a81f0
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12762
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Ionela Voinescu 2015-08-06 19:22:53 +01:00 committed by Martin Roth
parent fb5647a60b
commit f6d3bd4815
1 changed files with 2 additions and 2 deletions
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4
src/soc/imgtec/pistachio/include/soc/memlayout.ld
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@ -26,8 +26,8 @@ SECTIONS
DRAM_START(0x00000000) DRAM_START(0x00000000)
/* DMA coherent area: accessed via KSEG1. */ /* DMA coherent area: accessed via KSEG1. */
DMA_COHERENT(0x00100000, 1M) DMA_COHERENT(0x00100000, 1M)
POSTRAM_CBFS_CACHE(0x00200000, 192K) POSTRAM_CBFS_CACHE(0x00200000, 512K)
RAMSTAGE(0x00230000, 128K) RAMSTAGE(0x00280000, 128K)
/* /*
* GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock * GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock