soc/amd/common/lpc: Add SuperIO decode function
The LPC-ISA bridge supports two ranges for SuperIO control registers. Add a generic function to allow a mainboard to enable the appropriate range. Provide #define values that are more descriptive than the register's field names. Change-Id: Ic5445cfc137604cb1bb3ee3ea4c3a4ebdb9a9cab Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35271 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -75,6 +75,8 @@
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#define LPC_WIDEIO0_ENABLE BIT(2)
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#define DECODE_ALTERNATE_SIO_ENABLE BIT(1)
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#define DECODE_SIO_ENABLE BIT(0)
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#define LPC_SELECT_SIO_4E4F 1
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#define LPC_SELECT_SIO_2E2F 0
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#define WIDEIO_RANGE_ERROR -1
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/* Assuming word access to higher word (register 0x4a) */
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@ -151,6 +153,8 @@ void soc_late_lpc_bridge_enable(void);
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void lpc_enable_port80(void);
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void lpc_enable_pci_port80(void);
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void lpc_enable_decode(uint32_t decodes);
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/* addr = index/data to enable: LPC_SELECT_SIO_2E2F or LPC_SELECT_SIO_4E4F */
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void lpc_enable_sio_decode(const bool addr);
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uintptr_t lpc_spibase(void);
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void lpc_tpm_decode(void);
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void lpc_tpm_decode_spi(void);
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@ -165,6 +165,18 @@ void lpc_enable_pci_port80(void)
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pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte);
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}
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void lpc_enable_sio_decode(const bool addr)
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{
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uint32_t decodes;
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uint32_t enable;
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decodes = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE);
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enable = addr == LPC_SELECT_SIO_2E2F ?
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DECODE_SIO_ENABLE : DECODE_ALTERNATE_SIO_ENABLE;
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decodes |= enable;
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pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, decodes);
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}
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void lpc_enable_decode(uint32_t decodes)
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{
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pci_write_config32(_LPCB_DEV, LPC_IO_PORT_DECODE_ENABLE, decodes);
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