southbridge/amd/rsXY0/cmn.c: Trivial - Style fixes
Remove some ASCII art past 80 columns. Change-Id: I00ad79f2e1ddd78935efcfab19d9e166f0349ae3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6155 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Edward O'Callaghan
parent
7116ac8037
commit
f6e1cbec2a
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@ -47,7 +47,7 @@ static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
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/* extension registers */
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u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
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{
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/*get BAR3 base address for nbcfg0x1c */
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/* get BAR3 base address for nbcfg0x1c */
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u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
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printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
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dev->path.pci.devfn);
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@ -60,7 +60,7 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask
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{
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u32 reg_old, reg;
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/*get BAR3 base address for nbcfg0x1c */
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/* get BAR3 base address for nbcfg0x1c */
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u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
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/*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
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dev->path.pci.devfn);*/
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@ -191,12 +191,12 @@ void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)
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}
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}
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/***********************************************************
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* To access bar3 we need to program PCI MMIO 7 in K8.
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* in_out:
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* 1: enable/enter k8 temp mmio base
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* 0: disable/restore
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***********************************************************/
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/*
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* To access bar3 we need to program PCI MMIO 7 in K8.
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* in_out:
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* 1: enable/enter k8 temp mmio base
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* 0: disable/restore
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*/
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void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
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{
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/* K8 Function1 is address map */
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@ -245,11 +245,11 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
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}
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}
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/********************************************************************************************************
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* Output:
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* 0: no device is present.
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* 1: device is present and is trained.
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********************************************************************************************************/
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/*
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* Output:
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* 0: no device is present.
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* 1: device is present and is trained.
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*/
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u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
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{
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u16 count = 5000;
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@ -278,17 +278,13 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
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count = 0;
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break;
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case 0x10:
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reg =
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pci_ext_read_config32(nb_dev, dev,
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PCIE_VC0_RESOURCE_STATUS);
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reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS);
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printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg);
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/* check bit1 */
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if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */
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/* set bit8=1, bit0-2=bit4-6 */
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u32 tmp;
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reg =
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nbpcie_p_read_index(dev,
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PCIE_LC_LINK_WIDTH);
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reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH);
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tmp = (reg >> 4) && 0x3; /* get bit4-6 */
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reg &= 0xfff8; /* clear bit0-2 */
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reg += tmp; /* merge */
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@ -309,9 +305,9 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
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}
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/*
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* Compliant with CIM_33's ATINB_SetToms.
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* Set Top Of Memory below and above 4G.
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*/
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* Compliant with CIM_33's ATINB_SetToms.
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* Set Top Of Memory below and above 4G.
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*/
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void rs690_set_tom(device_t nb_dev)
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{
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/* set TOM */
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@ -46,7 +46,7 @@ static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
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/* extension registers */
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u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
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{
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/*get BAR3 base address for nbcfg0x1c */
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/* get BAR3 base address for nbcfg0x1c */
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u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
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printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
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dev->path.pci.devfn);
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@ -59,7 +59,7 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask
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{
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u32 reg_old, reg;
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/*get BAR3 base address for nbcfg0x1c */
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/* get BAR3 base address for nbcfg0x1c */
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u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
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/*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
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dev->path.pci.devfn);*/
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@ -190,12 +190,12 @@ void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)
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}
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}
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/***********************************************************
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* To access bar3 we need to program PCI MMIO 7 in K8.
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* in_out:
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* 1: enable/enter k8 temp mmio base
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* 0: disable/restore
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***********************************************************/
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/*
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* To access bar3 we need to program PCI MMIO 7 in K8.
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* in_out:
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* 1: enable/enter k8 temp mmio base
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* 0: disable/restore
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*/
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void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
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{
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/* K8 Function1 is address map */
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@ -249,11 +249,11 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
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}
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}
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/********************************************************************************************************
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* Output:
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* 0: no device is present.
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* 1: device is present and is trained.
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********************************************************************************************************/
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/*
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* Output:
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* 0: no device is present.
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* 1: device is present and is trained.
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*/
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u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
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{
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u16 count = 5000;
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@ -319,17 +319,13 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
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count = 0;
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break;
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case 0x10:
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reg =
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pci_ext_read_config32(nb_dev, dev,
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PCIE_VC0_RESOURCE_STATUS);
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reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS);
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printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg);
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/* check bit1 */
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if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */
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/* set bit8=1, bit0-2=bit4-6 */
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u32 tmp;
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reg =
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nbpcie_p_read_index(dev,
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PCIE_LC_LINK_WIDTH);
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reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH);
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tmp = (reg >> 4) && 0x3; /* get bit4-6 */
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reg &= 0xfff8; /* clear bit0-2 */
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reg += tmp; /* merge */
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@ -350,9 +346,9 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
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}
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/*
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* Compliant with CIM_33's ATINB_SetToms.
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* Set Top Of Memory below and above 4G.
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*/
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* Compliant with CIM_33's ATINB_SetToms.
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* Set Top Of Memory below and above 4G.
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*/
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void rs780_set_tom(device_t nb_dev)
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{
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/* set TOM */
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