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southbridge/amd/rsXY0/cmn.c: Trivial - Style fixes 

Remove some ASCII art past 80 columns.

Change-Id: I00ad79f2e1ddd78935efcfab19d9e166f0349ae3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6155
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Edward O'Callaghan 2014-06-28 22:47:22 +10:00
parent 7116ac8037
commit f6e1cbec2a
2 changed files with 36 additions and 44 deletions
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16
src/southbridge/amd/rs690/cmn.c
View File

@ -191,12 +191,12 @@ void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)
}
}
/***********************************************************
/*
* To access bar3 we need to program PCI MMIO 7 in K8.
* in_out:
* 1: enable/enter k8 temp mmio base
* 0: disable/restore
***********************************************************/
*/
void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
{
/* K8 Function1 is address map */
@ -245,11 +245,11 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
}
}
/********************************************************************************************************
/*
* Output:
* 0: no device is present.
* 1: device is present and is trained.
********************************************************************************************************/
*/
u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
{
u16 count = 5000;
@ -278,17 +278,13 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
count = 0;
break;
case 0x10:
reg =
pci_ext_read_config32(nb_dev, dev,
PCIE_VC0_RESOURCE_STATUS);
reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS);
printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg);
/* check bit1 */
if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */
/* set bit8=1, bit0-2=bit4-6 */
u32 tmp;
reg =
nbpcie_p_read_index(dev,
PCIE_LC_LINK_WIDTH);
reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH);
tmp = (reg >> 4) && 0x3; /* get bit4-6 */
reg &= 0xfff8; /* clear bit0-2 */
reg += tmp; /* merge */

16
src/southbridge/amd/rs780/cmn.c
View File

@ -190,12 +190,12 @@ void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)
}
}
/***********************************************************
/*
* To access bar3 we need to program PCI MMIO 7 in K8.
* in_out:
* 1: enable/enter k8 temp mmio base
* 0: disable/restore
***********************************************************/
*/
void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
{
/* K8 Function1 is address map */
@ -249,11 +249,11 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
}
}
/********************************************************************************************************
/*
* Output:
* 0: no device is present.
* 1: device is present and is trained.
********************************************************************************************************/
*/
u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
{
u16 count = 5000;
@ -319,17 +319,13 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
count = 0;
break;
case 0x10:
reg =
pci_ext_read_config32(nb_dev, dev,
PCIE_VC0_RESOURCE_STATUS);
reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS);
printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg);
/* check bit1 */
if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */
/* set bit8=1, bit0-2=bit4-6 */
u32 tmp;
reg =
nbpcie_p_read_index(dev,
PCIE_LC_LINK_WIDTH);
reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH);
tmp = (reg >> 4) && 0x3; /* get bit4-6 */
reg &= 0xfff8; /* clear bit0-2 */
reg += tmp; /* merge */