Disable dev3 on ma78gm-us2h
Disable bus 0 dev 3 PCI bridge, ma78gm-us2h does not have this slot. Change-Id: Ia355ee385fd0f37793b4bdf1815c033670823eaa Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/187 Tested-by: build bot (Jenkins)
This commit is contained in:
parent
0e8ee81edb
commit
f6e37316d0
|
@ -13,7 +13,7 @@ chip northbridge/amd/amdfam10/root_complex
|
||||||
device pci 0.0 on end # HT 0x9600
|
device pci 0.0 on end # HT 0x9600
|
||||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
|
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
|
||||||
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
|
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
|
||||||
device pci 3.0 on end # PCIE P2P bridge 0x960b
|
device pci 3.0 off end # PCIE P2P bridge 0x960b
|
||||||
device pci 4.0 on end # PCIE P2P bridge 0x9604
|
device pci 4.0 on end # PCIE P2P bridge 0x9604
|
||||||
device pci 5.0 off end # PCIE P2P bridge 0x9605
|
device pci 5.0 off end # PCIE P2P bridge 0x9605
|
||||||
device pci 6.0 off end # PCIE P2P bridge 0x9606
|
device pci 6.0 off end # PCIE P2P bridge 0x9606
|
||||||
|
|
Loading…
Reference in New Issue