diff --git a/src/mainboard/google/brya/variants/craask/gpio.c b/src/mainboard/google/brya/variants/craask/gpio.c
index bebc8d2138..9ccb57a5e7 100644
--- a/src/mainboard/google/brya/variants/craask/gpio.c
+++ b/src/mainboard/google/brya/variants/craask/gpio.c
@@ -13,7 +13,7 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
 	/* D6  : WWAN_EN */
 	PAD_CFG_GPO(GPP_D6, 1, DEEP),
-	/* D7  : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */
+	/* D7  : SRCCLKREQ2# ==> SSD_CLKREQ_ODL */
 	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
 	/* D11 : EN_PP3300_SSD */
 	PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG),
diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb
index 45078c92d0..5b9bf80066 100644
--- a/src/mainboard/google/brya/variants/craask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/craask/overridetree.cb
@@ -502,9 +502,12 @@ chip soc/intel/alderlake
 			probe SD_CARD SD_GL9750S
 		end
 		device ref pcie_rp9 on
-			# Enable NVMe SSD PCIe 9-12 using clk 2
+			# Enable NVMe SSD PCIe 9-12 using clk_src1 and clk_req2 mapping to hardware
+			# design.Due to inconsistency between PMC firmware and FSP, we need to set
+			# clk_src to clk_req number, not same as hardware mapping in coreboot.Then
+			# swap correct setting to clk_src=1,clk_req=2 in mFIT.
 			register "pch_pcie_rp[PCH_RP(9)]" = "{
-				.clk_src = 1,
+				.clk_src = 2,
 				.clk_req = 2,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"