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soc/intel/jasperlake: Enable VT-d and generate DMAR Table 

Update UPDs required for the creation of DMAR table.

By default coreboot was not generating DMAR table for IOMMU which
was resulting in below error message in kernel:
DMAR: [Firmware Bug]: No DRHD structure found in DMAR table
DMAR: No DMAR devices found
These changes will publish DMAR table through ACPI and will not
result in the above error.

BUG=b:170261791
BRANCH=dedede
TEST=Build Dedede, boot to kernel and check dmesg if DMAR
     table exists.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I97a9f2df185002a4e58eaa910f867acd0b97ec2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
This commit is contained in:
Meera Ravindranath 2020-11-12 16:29:24 +05:30 committed by Subrata Banik
parent 99eed832ae
commit f71572605a
1 changed files with 13 additions and 0 deletions
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13
src/soc/intel/jasperlake/romstage/fsp_params.c
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@ -4,6 +4,7 @@
#include <console/console.h>
#include <device/device.h>
#include <fsp/util.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
#include <soc/soc_chip.h>
@ -81,6 +82,18 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
/* VT-d config */
m_cfg->VtdDisable = 0;
m_cfg->VtdIopEnable = 0x1;
if (m_cfg->InternalGfx) {
m_cfg->VtdIgdEnable = 0x1;
m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
}
if (m_cfg->SaIpuEnable) {
m_cfg->VtdIpuEnable = 0x1;
m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS;
}
m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS;
m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
m_cfg->SerialIoUartDebugMode = config->SerialIoUartMode[CONFIG_UART_FOR_CONSOLE];