soc/tigerlake: Add IRQ header and ACPI support for JSP
Tigerlake irq.h and pci_irqs.asl have differences compared to Jasperlake. Hence renaming irq.h as irq_tgl.h and pci_irqs.asl as pci_irqs_tgl.asl Also adding a new file irq_jsl.h and pci_irqs_jsl.asl for Jasperlake SoC and allowing irq.h and pci_irqs.asl to choose the correct file based on SoC selected. BUG=None BRANCH=None TEST=Compilation for Jasperlake board is working Change-Id: Ia8e88f92929fe40d7be1c28947e005cb0d862fcb Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
This commit is contained in:
Meera Ravindranath
Patrick Georgi
parent
5efe122b27
commit
f71c6ae216
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@ -14,155 +14,8 @@
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* GNU General Public License for more details.
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*/
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#include <soc/irq.h>
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Name (PICP, Package () {
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/* D31:HSA, SMBUS, TraceHUB */
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Package(){0x001FFFFF, 3, 0, HDA_IRQ },
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Package(){0x001FFFFF, 4, 0, SMBUS_IRQ },
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Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ },
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/* D30: UART0, UART1, SPI0, SPI1 */
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Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
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Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
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Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
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Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
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/* D29: RP9 ~ RP12 */
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Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ },
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Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ },
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Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ },
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Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ },
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/* D28: RP1 ~ RP8 */
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Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
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Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
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Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
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Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
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Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
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Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ },
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Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
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Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
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/* D25: I2C4, I2C5, UART2 */
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Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
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Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
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Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
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/* D23: SATA */
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Package(){0x0017FFFF, 0, 0, SATA_IRQ },
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/* D22: CSME */
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Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
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Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
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Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
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Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
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/* D21: I2C0 ~ I2C3 */
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Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
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Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
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Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
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Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
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/* D20: xHCI, xDCI, SRAM, CNVI_WIFI */
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Package(){0x0014FFFF, 0, 0, xHCI_IRQ },
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Package(){0x0014FFFF, 1, 0, xDCI_IRQ },
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Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ },
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/* D19: SPI3 */
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Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ },
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/* D18: ISH, SPI2 */
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Package(){0x0012FFFF, 0, 0, ISH_IRQ },
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Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
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/* D16: CNVI_BT, TCH0, TCH1 */
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Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ },
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Package(){0x0010FFFF, 6, 0, THC0_IRQ },
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Package(){0x0010FFFF, 7, 0, THC1_IRQ },
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/* D13: xHCI, xDCI */
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Package(){0x000DFFFF, 0, 0, xHCI_IRQ },
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Package(){0x000DFFFF, 1, 0, xDCI_IRQ },
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/* D8: GNA */
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Package(){0x0008FFFF, 0, 0, GNA_IRQ },
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/* D7: TBT PCIe */
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Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ },
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Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ },
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Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ },
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Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ },
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/* D6: PEG60 */
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Package(){0x0006FFFF, 0, 0, PEG_IRQ },
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/* D5: IPU Device */
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Package(){0x0005FFFF, 0, 0, IPU_IRQ },
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/* D4: Thermal Device */
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Package(){0x0004FFFF, 0, 0, THERMAL_IRQ },
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/* D2: IGFX */
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Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
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})
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Name (PICN, Package () {
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/* D31:HSA, SMBUS, TraceHUB*/
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Package () { 0x001FFFFF, 3, 0, 11 },
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Package () { 0x001FFFFF, 4, 0, 11 },
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Package () { 0x001FFFFF, 7, 0, 11 },
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/* D30: UART0, UART1, SPI0, SPI1 */
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Package () { 0x001EFFFF, 0, 0, 11 },
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Package () { 0x001EFFFF, 1, 0, 10 },
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Package () { 0x001EFFFF, 2, 0, 11 },
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Package () { 0x001EFFFF, 3, 0, 11 },
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/* D29: RP9 ~ RP12 */
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Package () { 0x001DFFFF, 0, 0, 11 },
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Package () { 0x001DFFFF, 1, 0, 10 },
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Package () { 0x001DFFFF, 2, 0, 11 },
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Package () { 0x001DFFFF, 3, 0, 11 },
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/* D28: RP1 ~ RP8 */
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Package () { 0x001CFFFF, 0, 0, 11 },
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Package () { 0x001CFFFF, 1, 0, 10 },
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Package () { 0x001CFFFF, 2, 0, 11 },
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Package () { 0x001CFFFF, 3, 0, 11 },
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Package () { 0x001CFFFF, 4, 0, 11 },
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Package () { 0x001CFFFF, 5, 0, 10 },
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Package () { 0x001CFFFF, 6, 0, 11 },
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Package () { 0x001CFFFF, 7, 0, 11 },
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/* D25: I2C4, I2C5, UART2 */
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Package(){0x0019FFFF, 0, 0, 11 },
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Package(){0x0019FFFF, 1, 0, 10 },
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Package(){0x0019FFFF, 2, 0, 11 },
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/* D23: SATA */
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Package () { 0x0017FFFF, 0, 0, 11 },
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/* D22: CSME */
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Package(){0x0016FFFF, 0, 0, 11 },
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Package(){0x0016FFFF, 1, 0, 10 },
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Package(){0x0016FFFF, 4, 0, 11 },
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Package(){0x0016FFFF, 5, 0, 11 },
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/* D21: I2C0 ~ I2C3 */
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Package(){0x0015FFFF, 0, 0, 11 },
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Package(){0x0015FFFF, 1, 0, 10 },
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Package(){0x0015FFFF, 2, 0, 11 },
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Package(){0x0015FFFF, 3, 0, 11 },
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/* D19: SPI3 */
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Package(){0x0013FFFF, 0, 0, 11 },
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/* D18: ISH, SPI2 */
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Package(){0x0012FFFF, 0, 0, 11 },
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Package(){0x0012FFFF, 6, 0, 11 },,
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/* D16: CNVI_BT, TCH0, TCH1 */
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Package(){0x0010FFFF, 2, 0, 11 },
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Package(){0x0010FFFF, 6, 0, 11 },
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Package(){0x0010FFFF, 7, 0, 10 },
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/* D13: xHCI, xDCI */
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Package(){0x000DFFFF, 0, 0, 11 },
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Package(){0x000DFFFF, 1, 0, 10 },
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/* D8: GNA */
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Package(){0x0008FFFF, 0, 0, 11 },
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/* D7: TBT PCIe */
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Package(){0x0007FFFF, 0, 0, 11 },
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Package(){0x0007FFFF, 1, 0, 10 },
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Package(){0x0007FFFF, 2, 0, 11 },
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Package(){0x0007FFFF, 3, 0, 11 },
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/* D6: PEG60 */
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Package(){0x0006FFFF, 0, 0, 11 },
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/* D5: IPU Device */
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Package(){0x0005FFFF, 0, 0, 11 },
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/* D4: Thermal Device */
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Package(){0x0004FFFF, 0, 0, 11 },
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/* D2: IGFX */
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Package(){0x0002FFFF, 0, 0, 11 },
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})
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Method (_PRT)
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{
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If (PICM) {
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Return (^PICP)
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} Else {
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Return (^PICN)
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}
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}
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#if CONFIG(SOC_INTEL_TIGERLAKE)
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#include "pci_irqs_tgl.asl"
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#else
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#include "pci_irqs_jsl.asl"
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#endif
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@ -0,0 +1,142 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2020 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/irq.h>
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Name (PICP, Package () {
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/* cAVS, SMBus, GbE, Northpeak */
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Package(){0x001FFFFF, 3, 0, cAVS_INTA_IRQ },
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Package(){0x001FFFFF, 4, 0, SMBUS_INTB_IRQ },
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Package(){0x001FFFFF, 6, 0, GbE_INTC_IRQ },
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Package(){0x001FFFFF, 7, 0, TRACE_HUB_INTD_IRQ },
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/* SerialIo */
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Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
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Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
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Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
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Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
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/* PCI Express Port 1-8 */
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Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
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Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
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Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
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Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
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Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
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Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ },
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Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
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Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
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/* eMMC */
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Package(){0x001AFFFF, 0, 0, eMMC_IRQ },
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/* SerialIo */
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Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
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Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
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Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
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/* SATA controller */
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Package(){0x0017FFFF, 0, 0, SATA_IRQ },
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/* CSME (HECI, IDE-R, Keyboard and Text redirection */
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Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
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Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
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Package(){0x0016FFFF, 2, 0, IDER_IRQ },
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Package(){0x0016FFFF, 3, 0, KT_IRQ },
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Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
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Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
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/* SerialIo */
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Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
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Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
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Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
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Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
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/* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */
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Package(){0x0014FFFF, 0, 0, XHCI_IRQ },
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Package(){0x0014FFFF, 1, 0, OTG_IRQ },
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Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ },
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Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ },
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Package(){0x0014FFFF, 5, 0, SD_IRQ },
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/* SerialIo */
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Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
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/* SA IGFX Device */
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Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
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/* SA Thermal Device */
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Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ },
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/* SA IPU Device */
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Package(){0x0005FFFF, 0, 0, IPU_IRQ },
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/* SA GNA Device */
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Package(){0x0008FFFF, 0, 0, GNA_IRQ },
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})
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Name (PICN, Package () {
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/* D31: cAVS, SMBus, GbE, Northpeak */
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Package () { 0x001FFFFF, 3, 0, 11 },
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Package () { 0x001FFFFF, 4, 0, 10 },
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Package () { 0x001FFFFF, 6, 0, 11 },
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Package () { 0x001FFFFF, 7, 0, 11 },
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/* D30: SerialIo */
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Package () {0x001EFFFF, 0, 0, 11 },
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Package () {0x001EFFFF, 1, 0, 10 },
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Package () {0x001EFFFF, 2, 0, 11 },
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Package () {0x001EFFFF, 3, 0, 11 },
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/* D28: PCI Express Port 1-8 */
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Package () { 0x001CFFFF, 0, 0, 11 },
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Package () { 0x001CFFFF, 1, 0, 10 },
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Package () { 0x001CFFFF, 2, 0, 11 },
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Package () { 0x001CFFFF, 3, 0, 11 },
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Package () { 0x001CFFFF, 4, 0, 11 },
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Package () { 0x001CFFFF, 5, 0, 10 },
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Package () { 0x001CFFFF, 6, 0, 11 },
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Package () { 0x001CFFFF, 7, 0, 11 },
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/* D26: eMMC */
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Package(){0x001AFFFF, 0, 0, 11 },
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/* D25: SerialIo */
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Package () {0x0019FFFF, 0, 0, 11 },
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Package () {0x0019FFFF, 1, 0, 10 },
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Package () {0x0019FFFF, 2, 0, 11 },
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/* D23: SATA controller */
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Package () { 0x0017FFFF, 0, 0, 11 },
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/* D22: CSME (HECI, IDE-R, KT redirection */
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Package () { 0x0016FFFF, 0, 0, 11 },
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Package () { 0x0016FFFF, 1, 0, 10 },
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Package () { 0x0016FFFF, 2, 0, 11 },
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Package () { 0x0016FFFF, 3, 0, 11 },
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Package () { 0x0016FFFF, 4, 0, 11 },
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Package () { 0x0016FFFF, 5, 0, 11 },
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/* D21: SerialIo */
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Package () {0x0015FFFF, 0, 0, 11 },
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Package () {0x0015FFFF, 1, 0, 10 },
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Package () {0x0015FFFF, 2, 0, 11 },
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Package () {0x0015FFFF, 3, 0, 11 },
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/* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */
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Package () { 0x0014FFFF, 0, 0, 11 },
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Package () { 0x0014FFFF, 1, 0, 10 },
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Package () { 0x0014FFFF, 2, 0, 11 },
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Package () { 0x0014FFFF, 3, 0, 11 },
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Package () { 0x0014FFFF, 5, 0, 11 },
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/* D18: SerialIo */
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Package () {0x0012FFFF, 6, 0, 11 },
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/* SA IGFX Device */
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Package () {0x0002FFFF, 0, 0, 11 },
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/* SA Thermal Device */
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Package () { 0x0004FFFF, 0, 0, 11 },
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/* SA IPU Device */
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Package () { 0x0005FFFF, 0, 0, 11 },
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/* SA GNA Device */
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Package () { 0x0008FFFF, 0, 0, 11 },
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})
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Method (_PRT)
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{
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If (PICM) {
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Return (^PICP)
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} Else {
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Return (^PICN)
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}
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}
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@ -0,0 +1,168 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2020 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
|
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*
|
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/irq.h>
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Name (PICP, Package () {
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/* D31:HSA, SMBUS, TraceHUB */
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Package(){0x001FFFFF, 3, 0, HDA_IRQ },
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Package(){0x001FFFFF, 4, 0, SMBUS_IRQ },
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Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ },
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/* D30: UART0, UART1, SPI0, SPI1 */
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Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
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Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
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Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
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Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
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/* D29: RP9 ~ RP12 */
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Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ },
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Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ },
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Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ },
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Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ },
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/* D28: RP1 ~ RP8 */
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Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
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Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
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Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
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Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
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Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
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Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ },
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Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
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Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
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/* D25: I2C4, I2C5, UART2 */
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Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
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Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
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Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
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/* D23: SATA */
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Package(){0x0017FFFF, 0, 0, SATA_IRQ },
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/* D22: CSME */
|
||||
Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
|
||||
Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
|
||||
Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
|
||||
Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
|
||||
/* D21: I2C0 ~ I2C3 */
|
||||
Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
|
||||
Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
|
||||
Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
|
||||
Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
|
||||
/* D20: xHCI, xDCI, SRAM, CNVI_WIFI */
|
||||
Package(){0x0014FFFF, 0, 0, xHCI_IRQ },
|
||||
Package(){0x0014FFFF, 1, 0, xDCI_IRQ },
|
||||
Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ },
|
||||
/* D19: SPI3 */
|
||||
Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ },
|
||||
/* D18: ISH, SPI2 */
|
||||
Package(){0x0012FFFF, 0, 0, ISH_IRQ },
|
||||
Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
|
||||
/* D16: CNVI_BT, TCH0, TCH1 */
|
||||
Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ },
|
||||
Package(){0x0010FFFF, 6, 0, THC0_IRQ },
|
||||
Package(){0x0010FFFF, 7, 0, THC1_IRQ },
|
||||
/* D13: xHCI, xDCI */
|
||||
Package(){0x000DFFFF, 0, 0, xHCI_IRQ },
|
||||
Package(){0x000DFFFF, 1, 0, xDCI_IRQ },
|
||||
/* D8: GNA */
|
||||
Package(){0x0008FFFF, 0, 0, GNA_IRQ },
|
||||
/* D7: TBT PCIe */
|
||||
Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ },
|
||||
Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ },
|
||||
Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ },
|
||||
Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ },
|
||||
/* D6: PEG60 */
|
||||
Package(){0x0006FFFF, 0, 0, PEG_IRQ },
|
||||
/* D5: IPU Device */
|
||||
Package(){0x0005FFFF, 0, 0, IPU_IRQ },
|
||||
/* D4: Thermal Device */
|
||||
Package(){0x0004FFFF, 0, 0, THERMAL_IRQ },
|
||||
/* D2: IGFX */
|
||||
Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
|
||||
})
|
||||
|
||||
Name (PICN, Package () {
|
||||
/* D31:HSA, SMBUS, TraceHUB*/
|
||||
Package () { 0x001FFFFF, 3, 0, 11 },
|
||||
Package () { 0x001FFFFF, 4, 0, 11 },
|
||||
Package () { 0x001FFFFF, 7, 0, 11 },
|
||||
/* D30: UART0, UART1, SPI0, SPI1 */
|
||||
Package () { 0x001EFFFF, 0, 0, 11 },
|
||||
Package () { 0x001EFFFF, 1, 0, 10 },
|
||||
Package () { 0x001EFFFF, 2, 0, 11 },
|
||||
Package () { 0x001EFFFF, 3, 0, 11 },
|
||||
/* D29: RP9 ~ RP12 */
|
||||
Package () { 0x001DFFFF, 0, 0, 11 },
|
||||
Package () { 0x001DFFFF, 1, 0, 10 },
|
||||
Package () { 0x001DFFFF, 2, 0, 11 },
|
||||
Package () { 0x001DFFFF, 3, 0, 11 },
|
||||
/* D28: RP1 ~ RP8 */
|
||||
Package () { 0x001CFFFF, 0, 0, 11 },
|
||||
Package () { 0x001CFFFF, 1, 0, 10 },
|
||||
Package () { 0x001CFFFF, 2, 0, 11 },
|
||||
Package () { 0x001CFFFF, 3, 0, 11 },
|
||||
Package () { 0x001CFFFF, 4, 0, 11 },
|
||||
Package () { 0x001CFFFF, 5, 0, 10 },
|
||||
Package () { 0x001CFFFF, 6, 0, 11 },
|
||||
Package () { 0x001CFFFF, 7, 0, 11 },
|
||||
/* D25: I2C4, I2C5, UART2 */
|
||||
Package(){0x0019FFFF, 0, 0, 11 },
|
||||
Package(){0x0019FFFF, 1, 0, 10 },
|
||||
Package(){0x0019FFFF, 2, 0, 11 },
|
||||
/* D23: SATA */
|
||||
Package () { 0x0017FFFF, 0, 0, 11 },
|
||||
/* D22: CSME */
|
||||
Package(){0x0016FFFF, 0, 0, 11 },
|
||||
Package(){0x0016FFFF, 1, 0, 10 },
|
||||
Package(){0x0016FFFF, 4, 0, 11 },
|
||||
Package(){0x0016FFFF, 5, 0, 11 },
|
||||
/* D21: I2C0 ~ I2C3 */
|
||||
Package(){0x0015FFFF, 0, 0, 11 },
|
||||
Package(){0x0015FFFF, 1, 0, 10 },
|
||||
Package(){0x0015FFFF, 2, 0, 11 },
|
||||
Package(){0x0015FFFF, 3, 0, 11 },
|
||||
/* D19: SPI3 */
|
||||
Package(){0x0013FFFF, 0, 0, 11 },
|
||||
/* D18: ISH, SPI2 */
|
||||
Package(){0x0012FFFF, 0, 0, 11 },
|
||||
Package(){0x0012FFFF, 6, 0, 11 },,
|
||||
/* D16: CNVI_BT, TCH0, TCH1 */
|
||||
Package(){0x0010FFFF, 2, 0, 11 },
|
||||
Package(){0x0010FFFF, 6, 0, 11 },
|
||||
Package(){0x0010FFFF, 7, 0, 10 },
|
||||
/* D13: xHCI, xDCI */
|
||||
Package(){0x000DFFFF, 0, 0, 11 },
|
||||
Package(){0x000DFFFF, 1, 0, 10 },
|
||||
/* D8: GNA */
|
||||
Package(){0x0008FFFF, 0, 0, 11 },
|
||||
/* D7: TBT PCIe */
|
||||
Package(){0x0007FFFF, 0, 0, 11 },
|
||||
Package(){0x0007FFFF, 1, 0, 10 },
|
||||
Package(){0x0007FFFF, 2, 0, 11 },
|
||||
Package(){0x0007FFFF, 3, 0, 11 },
|
||||
/* D6: PEG60 */
|
||||
Package(){0x0006FFFF, 0, 0, 11 },
|
||||
/* D5: IPU Device */
|
||||
Package(){0x0005FFFF, 0, 0, 11 },
|
||||
/* D4: Thermal Device */
|
||||
Package(){0x0004FFFF, 0, 0, 11 },
|
||||
/* D2: IGFX */
|
||||
Package(){0x0002FFFF, 0, 0, 11 },
|
||||
})
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
If (PICM) {
|
||||
Return (^PICP)
|
||||
} Else {
|
||||
Return (^PICN)
|
||||
}
|
||||
}
|
||||
|
|
@ -16,69 +16,10 @@
|
|||
#ifndef _SOC_IRQ_H_
|
||||
#define _SOC_IRQ_H_
|
||||
|
||||
#define GPIO_IRQ14 14
|
||||
#define GPIO_IRQ15 15
|
||||
#if CONFIG(SOC_INTEL_TIGERLAKE)
|
||||
#include "irq_tgl.h"
|
||||
#else
|
||||
#include "irq_jsl.h"
|
||||
#endif /* CONFIG_SOC_INTEL_TIGERLAKE */
|
||||
|
||||
#define PCH_IRQ10 10
|
||||
#define PCH_IRQ11 11
|
||||
|
||||
#define LPSS_I2C0_IRQ 27
|
||||
#define LPSS_I2C1_IRQ 28
|
||||
#define LPSS_I2C2_IRQ 29
|
||||
#define LPSS_I2C3_IRQ 30
|
||||
#define LPSS_I2C4_IRQ 31
|
||||
#define LPSS_I2C5_IRQ 32
|
||||
#define LPSS_SPI0_IRQ 36
|
||||
#define LPSS_SPI1_IRQ 37
|
||||
#define LPSS_SPI2_IRQ 18
|
||||
#define LPSS_SPI3_IRQ 23
|
||||
#define LPSS_UART0_IRQ 34
|
||||
#define LPSS_UART1_IRQ 35
|
||||
#define LPSS_UART2_IRQ 33
|
||||
|
||||
#define HDA_IRQ 16
|
||||
#define SMBUS_IRQ 16
|
||||
#define TRACEHUB_IRQ 16
|
||||
|
||||
#define PCIE_1_IRQ 16
|
||||
#define PCIE_2_IRQ 17
|
||||
#define PCIE_3_IRQ 18
|
||||
#define PCIE_4_IRQ 19
|
||||
#define PCIE_5_IRQ 16
|
||||
#define PCIE_6_IRQ 17
|
||||
#define PCIE_7_IRQ 18
|
||||
#define PCIE_8_IRQ 19
|
||||
#define PCIE_9_IRQ 16
|
||||
#define PCIE_10_IRQ 17
|
||||
#define PCIE_11_IRQ 18
|
||||
#define PCIE_12_IRQ 19
|
||||
|
||||
#define SATA_IRQ 16
|
||||
|
||||
#define xHCI_IRQ 16
|
||||
#define xDCI_IRQ 17
|
||||
#define CNVI_WIFI_IRQ 16
|
||||
|
||||
#define CNVI_BT_IRQ 18
|
||||
|
||||
#define THC0_IRQ 16
|
||||
#define THC1_IRQ 17
|
||||
|
||||
#define ISH_IRQ 16
|
||||
|
||||
#define TBT_PCIe0_IRQ 16
|
||||
#define TBT_PCIe1_IRQ 17
|
||||
#define TBT_PCIe2_IRQ 18
|
||||
#define TBT_PCIe3_IRQ 19
|
||||
|
||||
#define HECI_1_IRQ 16
|
||||
#define HECI_2_IRQ 17
|
||||
#define HECI_3_IRQ 16
|
||||
#define HECI_4_IRQ 19
|
||||
|
||||
#define PEG_IRQ 16
|
||||
#define IGFX_IRQ 16
|
||||
#define THERMAL_IRQ 16
|
||||
#define IPU_IRQ 16
|
||||
#define GNA_IRQ 16
|
||||
#endif /* _SOC_IRQ_H_ */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2020 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _SOC_JSL_IRQ_H_
|
||||
#define _SOC_JSL_IRQ_H_
|
||||
|
||||
#define GPIO_IRQ14 14
|
||||
#define GPIO_IRQ15 15
|
||||
|
||||
#define PCH_IRQ10 10
|
||||
#define PCH_IRQ11 11
|
||||
|
||||
/* LPSS Devices */
|
||||
#define LPSS_I2C0_IRQ 16
|
||||
#define LPSS_I2C1_IRQ 17
|
||||
#define LPSS_I2C2_IRQ 18
|
||||
#define LPSS_I2C3_IRQ 19
|
||||
#define LPSS_I2C4_IRQ 32
|
||||
#define LPSS_I2C5_IRQ 33
|
||||
#define LPSS_SPI0_IRQ 22
|
||||
#define LPSS_SPI1_IRQ 23
|
||||
#define LPSS_SPI2_IRQ 24
|
||||
#define LPSS_UART0_IRQ 20
|
||||
#define LPSS_UART1_IRQ 21
|
||||
#define LPSS_UART2_IRQ 34
|
||||
|
||||
/* PCI D:31 F:x */
|
||||
#define cAVS_INTA_IRQ 16
|
||||
#define SMBUS_INTA_IRQ 16
|
||||
#define SMBUS_INTB_IRQ 17
|
||||
#define GbE_INTA_IRQ 16
|
||||
#define GbE_INTC_IRQ 18
|
||||
#define TRACE_HUB_INTA_IRQ 16
|
||||
#define TRACE_HUB_INTD_IRQ 19
|
||||
|
||||
/* PCI D:28 F:x */
|
||||
#define PCIE_1_IRQ 16
|
||||
#define PCIE_2_IRQ 17
|
||||
#define PCIE_3_IRQ 18
|
||||
#define PCIE_4_IRQ 19
|
||||
#define PCIE_5_IRQ 16
|
||||
#define PCIE_6_IRQ 17
|
||||
#define PCIE_7_IRQ 18
|
||||
#define PCIE_8_IRQ 19
|
||||
|
||||
/* PCI D:26 F:x */
|
||||
#define eMMC_IRQ 16
|
||||
|
||||
/* PCI D:23 F:x */
|
||||
#define SATA_IRQ 16
|
||||
|
||||
/* PCI D:22 F:x */
|
||||
#define HECI_1_IRQ 16
|
||||
#define HECI_2_IRQ 17
|
||||
#define HECI_3_IRQ 16
|
||||
#define HECI_4_IRQ 19
|
||||
#define IDER_IRQ 18
|
||||
#define KT_IRQ 19
|
||||
|
||||
/* PCI D:20 F:x */
|
||||
#define XHCI_IRQ 16
|
||||
#define OTG_IRQ 17
|
||||
#define CNViWIFI_IRQ 16
|
||||
#define SD_IRQ 19
|
||||
#define PMC_SRAM_IRQ 18
|
||||
|
||||
/* PCI D:18 F:x */
|
||||
#define UFS_IRQ 16
|
||||
|
||||
#define IGFX_IRQ 16
|
||||
#define SA_THERMAL_IRQ 16
|
||||
#define IPU_IRQ 16
|
||||
#define GNA_IRQ 16
|
||||
|
||||
#endif /* _JSL_IRQ_H_ */
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2020 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _SOC_TGL_IRQ_H_
|
||||
#define _SOC_TGL_IRQ_H_
|
||||
|
||||
#define GPIO_IRQ14 14
|
||||
#define GPIO_IRQ15 15
|
||||
|
||||
#define PCH_IRQ10 10
|
||||
#define PCH_IRQ11 11
|
||||
|
||||
#define LPSS_I2C0_IRQ 27
|
||||
#define LPSS_I2C1_IRQ 28
|
||||
#define LPSS_I2C2_IRQ 29
|
||||
#define LPSS_I2C3_IRQ 30
|
||||
#define LPSS_I2C4_IRQ 31
|
||||
#define LPSS_I2C5_IRQ 32
|
||||
#define LPSS_SPI0_IRQ 36
|
||||
#define LPSS_SPI1_IRQ 37
|
||||
#define LPSS_SPI2_IRQ 18
|
||||
#define LPSS_SPI3_IRQ 23
|
||||
#define LPSS_UART0_IRQ 34
|
||||
#define LPSS_UART1_IRQ 35
|
||||
#define LPSS_UART2_IRQ 33
|
||||
|
||||
#define HDA_IRQ 16
|
||||
#define SMBUS_IRQ 16
|
||||
#define TRACEHUB_IRQ 16
|
||||
|
||||
#define PCIE_1_IRQ 16
|
||||
#define PCIE_2_IRQ 17
|
||||
#define PCIE_3_IRQ 18
|
||||
#define PCIE_4_IRQ 19
|
||||
#define PCIE_5_IRQ 16
|
||||
#define PCIE_6_IRQ 17
|
||||
#define PCIE_7_IRQ 18
|
||||
#define PCIE_8_IRQ 19
|
||||
#define PCIE_9_IRQ 16
|
||||
#define PCIE_10_IRQ 17
|
||||
#define PCIE_11_IRQ 18
|
||||
#define PCIE_12_IRQ 19
|
||||
|
||||
#define SATA_IRQ 16
|
||||
|
||||
#define xHCI_IRQ 16
|
||||
#define xDCI_IRQ 17
|
||||
#define CNVI_WIFI_IRQ 16
|
||||
|
||||
#define CNVI_BT_IRQ 18
|
||||
|
||||
#define THC0_IRQ 16
|
||||
#define THC1_IRQ 17
|
||||
|
||||
#define ISH_IRQ 16
|
||||
|
||||
#define TBT_PCIe0_IRQ 16
|
||||
#define TBT_PCIe1_IRQ 17
|
||||
#define TBT_PCIe2_IRQ 18
|
||||
#define TBT_PCIe3_IRQ 19
|
||||
|
||||
#define HECI_1_IRQ 16
|
||||
#define HECI_2_IRQ 17
|
||||
#define HECI_3_IRQ 16
|
||||
#define HECI_4_IRQ 19
|
||||
|
||||
#define PEG_IRQ 16
|
||||
#define IGFX_IRQ 16
|
||||
#define THERMAL_IRQ 16
|
||||
#define IPU_IRQ 16
|
||||
#define GNA_IRQ 16
|
||||
#endif /* _TGL_IRQ_H_ */
|
||||
Loading…
Reference in New Issue