graysreef: update platform information

Some of the Lynx Point ids were off. Correct those and make
the pei data BAR fields consistent with the others.

Change-Id: I4102439588362cdb94643bd1ce69c9fa4278329e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2622
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/mainboard/intel/graysreef/romstage.c

@@ -135,7 +135,7 @@ void main(unsigned long bist)
 		mchbar: DEFAULT_MCHBAR,
 		dmibar: DEFAULT_DMIBAR,
 		epbar: DEFAULT_EPBAR,
-		pciexbar: CONFIG_MMCONF_BASE_ADDRESS,
+		pciexbar: DEFAULT_PCIEXBAR,
 		smbusbar: SMBUS_IO_BASE,
 		wdbbar: 0x4000000,
 		wdbsize: 0x1000,

src/northbridge/intel/haswell/report_platform.c

@@ -74,10 +74,11 @@ static struct {
 } pch_table [] = {
 	{0x8c41, "Mobile Engineering Sample"},
 	{0x8c42, "Desktop Engineering Sample"},
-	{0x8c46, "Z87"},
-	{0x8c49, "Z85"},
-	{0x8c4a, "HM86"},
-	{0x8c4b, "H87"},
+	{0x8c44, "Z87"},
+	{0x8c46, "Z85"},
+	{0x8c49, "HM86"},
+	{0x8c4a, "H87"},
+	{0x8c4b, "HM87"},
 	{0x8c4c, "Q85"},
 	{0x8c4e, "Q87"},
 	{0x8c4f, "QM87"},