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graysreef: update platform information 

Some of the Lynx Point ids were off. Correct those and make
the pei data BAR fields consistent with the others.

Change-Id: I4102439588362cdb94643bd1ce69c9fa4278329e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2622
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Aaron Durbin 2012-11-02 09:19:43 -05:00 committed by Stefan Reinauer
parent 4412bc4ae8
commit f72ad02158
2 changed files with 6 additions and 5 deletions
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2
src/mainboard/intel/graysreef/romstage.c
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@ -135,7 +135,7 @@ void main(unsigned long bist)
mchbar: DEFAULT_MCHBAR, mchbar: DEFAULT_MCHBAR,
dmibar: DEFAULT_DMIBAR, dmibar: DEFAULT_DMIBAR,
epbar: DEFAULT_EPBAR, epbar: DEFAULT_EPBAR,
pciexbar: CONFIG_MMCONF_BASE_ADDRESS, pciexbar: DEFAULT_PCIEXBAR,
smbusbar: SMBUS_IO_BASE, smbusbar: SMBUS_IO_BASE,
wdbbar: 0x4000000, wdbbar: 0x4000000,
wdbsize: 0x1000, wdbsize: 0x1000,

9
src/northbridge/intel/haswell/report_platform.c
View File

@ -74,10 +74,11 @@ static struct {
} pch_table [] = { } pch_table [] = {
{0x8c41, "Mobile Engineering Sample"}, {0x8c41, "Mobile Engineering Sample"},
{0x8c42, "Desktop Engineering Sample"}, {0x8c42, "Desktop Engineering Sample"},
{0x8c46, "Z87"}, {0x8c44, "Z87"},
{0x8c49, "Z85"}, {0x8c46, "Z85"},
{0x8c4a, "HM86"}, {0x8c49, "HM86"},
{0x8c4b, "H87"}, {0x8c4a, "H87"},
{0x8c4b, "HM87"},
{0x8c4c, "Q85"}, {0x8c4c, "Q85"},
{0x8c4e, "Q87"}, {0x8c4e, "Q87"},
{0x8c4f, "QM87"}, {0x8c4f, "QM87"},