GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/brask/var/kuldax: Set power limit values for RPL SKUs 

Add the RPL CPU power limits and system power limits based on
the suggestion of the thermal team for RPL SKUs.

The PL4 value suggested by the thermal team which is different from the reference document 686872.

BUG=b:292471206
BRANCH=firmware-brya-14505.B
TEST=built and booted into OS.

Change-Id: Ia030d13ca276c5e8340ae3b20d6e169bb162751d
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76769
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
This commit is contained in:
David Wu 2023-07-28 11:08:56 +08:00 committed by Matt DeVillier
parent 9faf74ca96
commit f731132fa0
2 changed files with 15 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/google/brya/variants/kuldax/overridetree.cb
View File

@ -51,6 +51,12 @@ chip soc/intel/alderlake
[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}" }"
register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 55,
.tdp_pl4 = 100,
}"
device domain 0 on device domain 0 on
device ref dtt on device ref dtt on
chip drivers/intel/dptf chip drivers/intel/dptf

9
src/mainboard/google/brya/variants/kuldax/ramstage.c
View File

@ -16,6 +16,9 @@ const struct cpu_power_limits limits[] = {
{ PCI_DID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 55000, 55000, 123000 }, { PCI_DID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 55000, 55000, 123000 },
{ PCI_DID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 140000 }, { PCI_DID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 140000 },
{ PCI_DID_INTEL_ADL_P_ID_3, 28, 28000, 28000, 64000, 64000, 140000 }, { PCI_DID_INTEL_ADL_P_ID_3, 28, 28000, 28000, 64000, 64000, 140000 },
{ PCI_DID_INTEL_RPL_P_ID_5, 15, 15000, 15000, 55000, 55000, 100000 },
{ PCI_DID_INTEL_RPL_P_ID_4, 15, 15000, 15000, 55000, 55000, 100000 },
{ PCI_DID_INTEL_RPL_P_ID_3, 15, 15000, 15000, 55000, 55000, 100000 },
}; };
const struct system_power_limits sys_limits[] = { const struct system_power_limits sys_limits[] = {
@ -25,6 +28,9 @@ const struct system_power_limits sys_limits[] = {
{ PCI_DID_INTEL_ADL_P_ID_6, 15, 225 }, { PCI_DID_INTEL_ADL_P_ID_6, 15, 225 },
{ PCI_DID_INTEL_ADL_P_ID_5, 28, 225 }, { PCI_DID_INTEL_ADL_P_ID_5, 28, 225 },
{ PCI_DID_INTEL_ADL_P_ID_3, 28, 225 }, { PCI_DID_INTEL_ADL_P_ID_3, 28, 225 },
{ PCI_DID_INTEL_RPL_P_ID_5, 15, 138 },
{ PCI_DID_INTEL_RPL_P_ID_4, 15, 138 },
{ PCI_DID_INTEL_RPL_P_ID_3, 15, 138 },
}; };
const struct system_power_limits revise_sys_limits[] = { const struct system_power_limits revise_sys_limits[] = {
@ -34,6 +40,9 @@ const struct system_power_limits revise_sys_limits[] = {
{ PCI_DID_INTEL_ADL_P_ID_6, 15, 225 }, { PCI_DID_INTEL_ADL_P_ID_6, 15, 225 },
{ PCI_DID_INTEL_ADL_P_ID_5, 28, 225 }, { PCI_DID_INTEL_ADL_P_ID_5, 28, 225 },
{ PCI_DID_INTEL_ADL_P_ID_3, 28, 225 }, { PCI_DID_INTEL_ADL_P_ID_3, 28, 225 },
{ PCI_DID_INTEL_RPL_P_ID_5, 15, 138 },
{ PCI_DID_INTEL_RPL_P_ID_4, 15, 138 },
{ PCI_DID_INTEL_RPL_P_ID_3, 15, 138 },
}; };
/* /*