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soc/intel/skylake: Enable bus master for sata 

The bus master needs to be enabled so that
the busy bit in AHCI PORT_TFDATA will be cleared
by controller when depthcharge tries to wait
for sata to complete spin-up during AHCI init.

Otherwise, the timeout will happen and cause
5 seconds delay in depthcharge.

BUG=b:37639063
BRANCH=none
TEST=verify that the sata timeout is gone in
     depthcharge

Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/21890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Kane Chen 2017-10-05 10:17:07 +08:00 committed by Aaron Durbin
parent 6754e4ea20
commit f73bc0b2d1
1 changed files with 5 additions and 0 deletions
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5
src/soc/intel/common/block/sata/sata.c
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@ -45,6 +45,11 @@ static void sata_final(device_t dev)
u32 port_impl, temp;
dev = PCH_DEV_SATA;
/* Set Bus Master */
temp = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER);
/* Read Ports Implemented (GHC_PI) */
port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED) & 0x07;
/* Port enable */