soc/intel/tigerlake: Add Hot-Plug and PME event handlers for Thunderbolt
This change adds Hot-Plug and power management event handers(_L61 & _L69) respectively for Thunderbolt in the GPE scope. The _L61 method invokes sub-method HPEV to support Hot-Plug wake event from Thunderbolt PCIe root ports. This method intercepts Presence Detect Changed interrupt and make sure the L0s is disabled on empty slots. The _L69 method checks and clears root port's PME SCI status. BUG=b:156435065 TEST=Verified multiple hot plug successfully with Lenovo dock. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I022cf4aa3f2ee459b9dc87849494e10755d995c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
John Zhao
Duncan Laurie
parent
a6e3b5ac09
commit
f74aa649b1
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@ -38,7 +38,7 @@ Scope (\_SB)
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Method (BASE, 1)
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Method (BASE, 1)
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{
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{
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Local0 = Arg0 & 0x7 /* Function number */
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Local0 = Arg0 & 0x7 /* Function number */
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Local1 = (Arg0 >> 16) & 0x1F /* Device number */
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Local1 = (Arg0 >> 16) & 0x1F /* Device number */
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Local2 = (Local0 << 12) + (Local1 << 15)
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Local2 = (Local0 << 12) + (Local1 << 15)
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Local3 = \_SB.PCI0.GPCB() + Local2
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Local3 = \_SB.PCI0.GPCB() + Local2
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Return (Local3)
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Return (Local3)
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@ -128,6 +128,127 @@ Scope (\_SB)
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}
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}
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}
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}
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Scope (_GPE)
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{
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/* PCI Express Hot-Plug wake event */
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Method (_L61, 0, NotSerialized)
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{
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/*
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* Delay for 100ms to meet the timing requirements of the PCI Express Base
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* Specification, Revision 1.0A, Section 6.6 ("...software must wait at least
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* 100ms from the end of reset of one or more device before it is permitted
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* to issue Configuration Requests to those devices").
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*/
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Sleep (100)
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If (CondRefOf (\_SB.PCI0.TXHC)) {
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/* Invoke PCIe root ports wake event handler */
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\_SB.PCI0.TRP0.HPEV()
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\_SB.PCI0.TRP1.HPEV()
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\_SB.PCI0.TRP2.HPEV()
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\_SB.PCI0.TRP3.HPEV()
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}
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/* Check Root Port 0 for a Hot Plug Event if the port is enabled */
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If (((\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP0.HPSX)) {
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If (\_SB.PCI0.TRP0.PDCX) {
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/* Clear all status bits */
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\_SB.PCI0.TRP0.PDCX = 1
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\_SB.PCI0.TRP0.HPSX = 1
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/*
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* Intercept Presence Detect Changed interrupt and make sure
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* the L0s is disabled on empty slots.
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*/
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If (!\_SB.PCI0.TRP0.PDSX) {
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/*
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* The PCIe slot is empty, so disable L0s on hot unplug.
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*/
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\_SB.PCI0.TRP0.L0SE = 0
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}
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/* Performs proper notification to the OS. */
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Notify (\_SB.PCI0.TRP0, 0)
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} Else {
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/* False event. Clear Hot-Plug status, then exit. */
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\_SB.PCI0.TRP0.HPSX = 1
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}
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}
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/* Check Root Port 1 for a Hot Plug Event if the port is enabled */
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If (((\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP1.HPSX)) {
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If (\_SB.PCI0.TRP1.PDCX) {
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\_SB.PCI0.TRP1.PDCX = 1
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\_SB.PCI0.TRP1.HPSX = 1
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If (!\_SB.PCI0.TRP1.PDSX) {
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\_SB.PCI0.TRP1.L0SE = 0
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}
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Notify (\_SB.PCI0.TRP1, 0)
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} Else {
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\_SB.PCI0.TRP1.HPSX = 1
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}
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}
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/* Check Root Port 2 for a Hot Plug Event if the port is enabled */
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If (((\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP2.HPSX)) {
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If (\_SB.PCI0.TRP2.PDCX) {
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\_SB.PCI0.TRP2.PDCX = 1
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\_SB.PCI0.TRP2.HPSX = 1
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If (!\_SB.PCI0.TRP2.PDSX) {
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\_SB.PCI0.TRP2.L0SE = 0
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}
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Notify (\_SB.PCI0.TRP2, 0)
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} Else {
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\_SB.PCI0.TRP2.HPSX = 1
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}
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}
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/* Check Root Port 3 for a Hot Plug Event if the port is enabled */
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If (((\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP3.HPSX)) {
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If (\_SB.PCI0.TRP3.PDCX) {
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\_SB.PCI0.TRP3.PDCX = 1
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\_SB.PCI0.TRP3.HPSX = 1
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If (!\_SB.PCI0.TRP3.PDSX) {
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\_SB.PCI0.TRP3.L0SE = 0
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}
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Notify (\_SB.PCI0.TRP3, 0)
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} Else {
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\_SB.PCI0.TRP3.HPSX = 1
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}
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}
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}
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/* PCI Express power management event */
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Method (_L69, 0, Serialized)
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{
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If (CondRefOf (\_SB.PCI0.TXHC)) {
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If (\_SB.PCI0.TRP0.HPME() == 1) {
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Notify (\_SB.PCI0.TDM0, 0x2)
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Notify (\_SB.PCI0.TRP0, 0x2)
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}
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If (\_SB.PCI0.TRP1.HPME() == 1) {
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Notify (\_SB.PCI0.TDM0, 0x2)
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Notify (\_SB.PCI0.TRP1, 0x2)
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}
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If (\_SB.PCI0.TRP2.HPME() == 1) {
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Notify (\_SB.PCI0.TDM1, 0x2)
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Notify (\_SB.PCI0.TRP2, 0x2)
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}
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If (\_SB.PCI0.TRP3.HPME() == 1) {
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Notify (\_SB.PCI0.TDM1, 0x2)
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Notify (\_SB.PCI0.TRP3, 0x2)
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}
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}
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/* Invoke PCIe root ports power management status handler */
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\_SB.PCI0.TRP0.HPME()
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\_SB.PCI0.TRP1.HPME()
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\_SB.PCI0.TRP2.HPME()
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\_SB.PCI0.TRP3.HPME()
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}
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}
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Scope (\_SB.PCI0)
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Scope (\_SB.PCI0)
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{
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{
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/*
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/*
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@ -320,48 +441,49 @@ Scope (\_SB.PCI0)
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{
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{
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If (\_SB.PCI0.TDM0.VDID == 0xFFFFFFFF) {
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If (\_SB.PCI0.TDM0.VDID == 0xFFFFFFFF) {
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Printf("TDM0 does not exist.")
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Printf("TDM0 does not exist.")
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}
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If (\_SB.PCI0.TDM0.STAT == 0) {
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/* DMA0 is in D3Cold early. */
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\_SB.PCI0.TDM0.D3CX() /* RTD3 Exit */
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Printf("Bring TBT RPs out of D3Code.")
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If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) {
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/* RP0 D3 cold exit. */
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\_SB.PCI0.TRP0.D3CX()
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}
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If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) {
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/* RP1 D3 cold exit. */
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\_SB.PCI0.TRP1.D3CX()
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}
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/*
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* Need to send Connect-Topology command when TBT host
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* controller back to D0 from D3.
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*/
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If (\_SB.PCI0.TDM0.ALCT == 1) {
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If (CTP0 == 1) {
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/*
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* Send Connect-Topology command if there is
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* device present on PCIe RP.
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*/
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\_SB.PCI0.TDM0.CNTP()
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/* Indicate to wait Connect-Topology command. */
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\_SB.PCI0.TDM0.WACT = 1
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/* Clear the connect states. */
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CTP0 = 0
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}
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/* Disallow to send Connect-Topology command. */
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\_SB.PCI0.TDM0.ALCT = 0
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}
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} Else {
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} Else {
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Printf("Drop TG0N due to it is already exit D3 cold.")
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If (\_SB.PCI0.TDM0.STAT == 0) {
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/* DMA0 is in D3Cold early. */
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\_SB.PCI0.TDM0.D3CX() /* RTD3 Exit */
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Printf("Bring TBT RPs out of D3Code.")
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If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) {
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/* RP0 D3 cold exit. */
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\_SB.PCI0.TRP0.D3CX()
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}
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If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) {
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/* RP1 D3 cold exit. */
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\_SB.PCI0.TRP1.D3CX()
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}
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/*
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* Need to send Connect-Topology command when TBT host
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* controller back to D0 from D3.
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*/
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If (\_SB.PCI0.TDM0.ALCT == 1) {
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If (CTP0 == 1) {
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/*
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* Send Connect-Topology command if there is
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* device present on PCIe RP.
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*/
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\_SB.PCI0.TDM0.CNTP()
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/* Indicate to wait Connect-Topology command. */
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\_SB.PCI0.TDM0.WACT = 1
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/* Clear the connect states. */
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CTP0 = 0
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}
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/* Disallow to send Connect-Topology command. */
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\_SB.PCI0.TDM0.ALCT = 0
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}
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} Else {
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Printf("Drop TG0N due to it is already exit D3 cold.")
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}
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/* TBT RTD3 exit 10ms delay. */
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Sleep (10)
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}
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}
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/* TBT RTD3 exit 10ms delay. */
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Sleep (10)
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}
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}
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/*
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/*
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@ -371,26 +493,26 @@ Scope (\_SB.PCI0)
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{
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{
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If (\_SB.PCI0.TDM0.VDID == 0xFFFFFFFF) {
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If (\_SB.PCI0.TDM0.VDID == 0xFFFFFFFF) {
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Printf("TDM0 does not exist.")
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Printf("TDM0 does not exist.")
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}
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} Else {
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If (\_SB.PCI0.TDM0.STAT == 1) {
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/* DMA0 is not in D3Cold now. */
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\_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */
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If (\_SB.PCI0.TDM0.STAT == 1) {
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Printf("Push TBT RPs to D3Cold together")
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/* DMA0 is not in D3Cold now. */
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If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) {
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\_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */
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If (\_SB.PCI0.TRP0.PDSX == 1) {
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CTP0 = 1
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Printf("Push TBT RPs to D3Cold together")
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}
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If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) {
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/* Put RP0 to D3 cold. */
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If (\_SB.PCI0.TRP0.PDSX == 1) {
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\_SB.PCI0.TRP0.D3CE()
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CTP0 = 1
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}
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}
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/* Put RP0 to D3 cold. */
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If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) {
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\_SB.PCI0.TRP0.D3CE()
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If (\_SB.PCI0.TRP1.PDSX == 1) {
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}
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CTP0 = 1
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If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) {
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}
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If (\_SB.PCI0.TRP1.PDSX == 1) {
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/* Put RP1 to D3 cold. */
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CTP0 = 1
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\_SB.PCI0.TRP1.D3CE()
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}
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}
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/* Put RP1 to D3 cold. */
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\_SB.PCI0.TRP1.D3CE()
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}
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}
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}
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}
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}
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}
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@ -402,48 +524,49 @@ Scope (\_SB.PCI0)
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{
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{
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If (\_SB.PCI0.TDM1.VDID == 0xFFFFFFFF) {
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If (\_SB.PCI0.TDM1.VDID == 0xFFFFFFFF) {
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Printf("TDM1 does not exist.")
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Printf("TDM1 does not exist.")
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}
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If (\_SB.PCI0.TDM1.STAT == 0) {
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/* DMA1 is in D3Cold early. */
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\_SB.PCI0.TDM1.D3CX() /* RTD3 Exit */
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Printf("Bring TBT RPs out of D3Code.")
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If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) {
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/* RP2 D3 cold exit. */
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\_SB.PCI0.TRP2.D3CX()
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}
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If (\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) {
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/* RP3 D3 cold exit. */
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\_SB.PCI0.TRP3.D3CX()
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}
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/*
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* Need to send Connect-Topology command when TBT host
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* controller back to D0 from D3.
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*/
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If (\_SB.PCI0.TDM1.ALCT == 1) {
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If (CTP1 == 1) {
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/*
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* Send Connect-Topology command if there is
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* device present on PCIe RP.
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*/
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\_SB.PCI0.TDM1.CNTP()
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/* Indicate to wait Connect-Topology command. */
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\_SB.PCI0.TDM1.WACT = 1
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/* Clear the connect states. */
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CTP1 = 0
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}
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/* Disallow to send Connect-Topology cmd. */
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\_SB.PCI0.TDM1.ALCT = 0
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}
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} Else {
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} Else {
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Printf("Drop TG1N due to it is already exit D3 cold.")
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If (\_SB.PCI0.TDM1.STAT == 0) {
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/* DMA1 is in D3Cold early. */
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\_SB.PCI0.TDM1.D3CX() /* RTD3 Exit */
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Printf("Bring TBT RPs out of D3Code.")
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If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) {
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/* RP2 D3 cold exit. */
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\_SB.PCI0.TRP2.D3CX()
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}
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If (\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) {
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/* RP3 D3 cold exit. */
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\_SB.PCI0.TRP3.D3CX()
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}
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/*
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* Need to send Connect-Topology command when TBT host
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* controller back to D0 from D3.
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*/
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If (\_SB.PCI0.TDM1.ALCT == 1) {
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If (CTP1 == 1) {
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/*
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* Send Connect-Topology command if there is
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* device present on PCIe RP.
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*/
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\_SB.PCI0.TDM1.CNTP()
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/* Indicate to wait Connect-Topology command. */
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\_SB.PCI0.TDM1.WACT = 1
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/* Clear the connect states. */
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CTP1 = 0
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}
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/* Disallow to send Connect-Topology cmd. */
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\_SB.PCI0.TDM1.ALCT = 0
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}
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} Else {
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Printf("Drop TG1N due to it is already exit D3 cold.")
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}
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/* TBT RTD3 exit 10ms delay. */
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Sleep (10)
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}
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}
|
||||||
/* TBT RTD3 exit 10ms delay. */
|
|
||||||
Sleep (10)
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
@ -453,26 +576,26 @@ Scope (\_SB.PCI0)
|
||||||
{
|
{
|
||||||
If (\_SB.PCI0.TDM1.VDID == 0xFFFFFFFF) {
|
If (\_SB.PCI0.TDM1.VDID == 0xFFFFFFFF) {
|
||||||
Printf("TDM1 does not exist.")
|
Printf("TDM1 does not exist.")
|
||||||
}
|
} Else {
|
||||||
|
If (\_SB.PCI0.TDM1.STAT == 1) {
|
||||||
|
/* DMA1 is not in D3Cold now */
|
||||||
|
\_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */
|
||||||
|
|
||||||
If (\_SB.PCI0.TDM1.STAT == 1) {
|
Printf("Push TBT RPs to D3Cold together")
|
||||||
/* DMA1 is not in D3Cold now */
|
If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) {
|
||||||
\_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */
|
If (\_SB.PCI0.TRP2.PDSX == 1) {
|
||||||
|
CTP1 = 1
|
||||||
Printf("Push TBT RPs to D3Cold together")
|
}
|
||||||
If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) {
|
/* Put RP2 to D3 cold. */
|
||||||
If (\_SB.PCI0.TRP2.PDSX == 1) {
|
\_SB.PCI0.TRP2.D3CE()
|
||||||
CTP1 = 1
|
|
||||||
}
|
}
|
||||||
/* Put RP2 to D3 cold. */
|
If (\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) {
|
||||||
\_SB.PCI0.TRP2.D3CE()
|
If (\_SB.PCI0.TRP3.PDSX == 1) {
|
||||||
}
|
CTP1 = 1
|
||||||
If (\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) {
|
}
|
||||||
If (\_SB.PCI0.TRP3.PDSX == 1) {
|
/* Put RP3 to D3 cold */
|
||||||
CTP1 = 1
|
\_SB.PCI0.TRP3.D3CE()
|
||||||
}
|
}
|
||||||
/* Put RP3 to D3 cold */
|
|
||||||
\_SB.PCI0.TRP3.D3CE()
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
@ -536,7 +659,7 @@ Scope (\_SB.PCI0)
|
||||||
}
|
}
|
||||||
|
|
||||||
If (Local0 == TCSS_IOM_ACK_TIMEOUT_IN_MS) {
|
If (Local0 == TCSS_IOM_ACK_TIMEOUT_IN_MS) {
|
||||||
Printf("Error: Error: Timeout occurred.")
|
Printf("Error: Timeout occurred.")
|
||||||
}
|
}
|
||||||
Else
|
Else
|
||||||
{
|
{
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue