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cpu: port amd/pi to 64bit 

Change-Id: I66ef081fa1a520f0199366587800783ea1ef8719
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11023
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Stefan Reinauer 2015-07-21 13:34:01 -07:00 committed by Stefan Reinauer
parent 42444f6f53
commit f7613ecacc
2 changed files with 69 additions and 1 deletions
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63
src/cpu/amd/pi/cache_as_ram.inc
View File

@ -64,10 +64,67 @@ cache_as_ram_setup:
cvtsi2sd %ebx, %xmm1
post_code(0xa1)
AMD_ENABLE_STACK
#ifdef __x86_64__
/* switch to 64 bit long mode */
.intel_syntax noprefix
post_code(0xa1)
mov ecx, esi
add ecx, 0 # core number
xor eax, eax
lea edi, [ecx+0x1000+0x23]
mov dword ptr [ecx+0], edi
mov dword ptr [ecx+4], eax
lea edi, [ecx+0x1000]
mov dword ptr [edi+0x00], 0x000000e3
mov dword ptr [edi+0x04], eax
mov dword ptr [edi+0x08], 0x400000e3
mov dword ptr [edi+0x0c], eax
mov dword ptr [edi+0x10], 0x800000e3
mov dword ptr [edi+0x14], eax
mov dword ptr [edi+0x18], 0xc00000e3
mov dword ptr [edi+0x1c], eax
# load rom based identity mapped page tables
mov eax, ecx
mov cr3,eax
# enable PAE
mov eax, cr4
bts eax, 5
mov cr4, eax
# enable long mode
mov ecx, 0xC0000080
rdmsr
bts eax, 8
wrmsr
# enable paging
mov eax, cr0
bts eax, 31
mov cr0, eax
# use call far to switch to 64-bit code segment
jmp 0x18,.+7
/* Pass the BIST result */
cvtsd2si esi, xmm1
/* Pass the cpu_init_detected */
cvtsd2si edi, xmm0
/* align the stack */
and esp, 0xFFFFFFF0
.code64
call cache_as_ram_main
.code32
.att_syntax prefix
#else
/* Restore the BIST result */
cvtsd2si %xmm0, %edx
@ -77,6 +134,7 @@ cache_as_ram_setup:
pushl %ebx /* init detected */
pushl %edx /* bist */
call cache_as_ram_main
#endif
/* Should never see this postcode */
post_code(0xaf)
@ -108,3 +166,6 @@ disable_cache_as_ram:
ret
cache_as_ram_setup_out:
#ifdef __x86_64__
.code64
#endif

7
src/cpu/amd/pi/s3_resume.c
View File

@ -164,10 +164,17 @@ static void move_stack_high_mem(void)
memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR,
(CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE));
#ifdef __x86_64__
__asm__
volatile ("add %0, %%rsp; add %0, %%rbp; invd"::"g"
(high_stack - BSP_STACK_BASE_ADDR)
:);
#else
__asm__
volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g"
(high_stack - BSP_STACK_BASE_ADDR)
:);
#endif
}
#endif