mediatek/mt8173: Add usb phy driver
BRANCH=none BUG=none TEST=build pass and test it ok on oak Change-Id: Ib3d3f420dd576a63d7504dd0949040a3d430c675 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b17b03ed40b562a520185fa243bc4458daed6f23 Original-Change-Id: Ib9346f7913433ca82e8123feaf34fd0d6c071047 Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292687 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13095 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Chunfeng Yun
Patrick Georgi
parent
cc248bcce3
commit
f764d1458d
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@ -64,6 +64,8 @@ ramstage-y += gpio.c
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ramstage-y += wdt.c
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ramstage-y += pll.c
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ramstage-y += usb.c
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################################################################################
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# Generate the actual coreboot bootblock code
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@ -0,0 +1,178 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SOC_MEDIATEK_MT8173_USB_H
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#define SOC_MEDIATEK_MT8173_USB_H
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/* ip_pw_ctrl0 */
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#define CTRL0_IP_SW_RST (0x1 << 0)
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/* ip_pw_ctrl1 */
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#define CTRL1_IP_HOST_PDN (0x1 << 0)
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/* ip_pw_sts1 */
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#define STS1_U3_MAC_RST (0x1 << 16)
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#define STS1_SYS125_RST (0x1 << 10)
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#define STS1_REF_RST (0x1 << 8)
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#define STS1_SYSPLL_STABLE (0x1 << 0)
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/* ip_pw_sts2 */
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#define STS2_U2_MAC_RST (0x1 << 0)
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/* ip_xhci_cap */
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#define CAP_U3_PORT_NUM(p) ((p) & 0xff)
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#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
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/* u3_ctrl_p */
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#define CTRL_U3_PORT_HOST_SEL (0x1 << 2)
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#define CTRL_U3_PORT_PDN (0x1 << 1)
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#define CTRL_U3_PORT_DIS (0x1 << 0)
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/* u2_ctrl_p */
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#define CTRL_U2_PORT_HOST_SEL (0x1 << 2)
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#define CTRL_U2_PORT_PDN (0x1 << 1)
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#define CTRL_U2_PORT_DIS (0x1 << 0)
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struct ssusb_ippc_regs {
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u32 ip_pw_ctr0;
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u32 ip_pw_ctr1;
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u32 ip_pw_ctr2;
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u32 ip_pw_ctr3;
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u32 ip_pw_sts1;
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u32 ip_pw_sts2;
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u32 reserved0[3];
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u32 ip_xhci_cap;
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u32 reserved1[2];
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u64 u3_ctrl_p[4];
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u64 u2_ctrl_p[6];
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};
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/* U2PHY_COM USBPHYACR5 */
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#define PA5_RG_U2_HSTX_SRCTRL (0x7 << 12)
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#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
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#define PA5_RG_U2_HS_100U_U3_EN (0x1 << 11)
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/* U2PHY_COM USBPHYACR6 */
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#define PA6_RG_U2_ISO_EN (0x1 << 31)
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#define PA6_RG_U2_BC11_SW_EN (0x1 << 23)
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#define PA6_RG_U2_OTG_VBUSCMP_EN (0x1 << 20)
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#define PA6_RG_U2_SQTH (0xf << 0)
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#define PA6_RG_U2_SQTH_VAL(x) ((0xf & (x)) << 0)
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/* U2PHY_COM U2PHYACR4 */
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#define P2C_RG_USB20_GPIO_CTL (0x1 << 9)
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#define P2C_USB20_GPIO_MODE (0x1 << 8)
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#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
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/* U2PHY_COM U2PHYDTM0 */
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#define P2C_FORCE_UART_EN (0x1 << 26)
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#define P2C_FORCE_DATAIN (0x1 << 23)
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#define P2C_FORCE_DM_PULLDOWN (0x1 << 21)
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#define P2C_FORCE_DP_PULLDOWN (0x1 << 20)
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#define P2C_FORCE_XCVRSEL (0x1 << 19)
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#define P2C_FORCE_SUSPENDM (0x1 << 18)
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#define P2C_FORCE_TERMSEL (0x1 << 17)
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#define P2C_RG_DATAIN (0xf << 10)
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#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10)
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#define P2C_RG_DMPULLDOWN (0x1 << 7)
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#define P2C_RG_DPPULLDOWN (0x1 << 6)
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#define P2C_RG_XCVRSEL (0x3 << 4)
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#define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4)
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#define P2C_RG_SUSPENDM (0x1 << 3)
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#define P2C_RG_TERMSEL (0x1 << 2)
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#define P2C_DTM0_PART_MASK \
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(P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
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P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
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P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
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P2C_RG_TERMSEL)
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/* U2PHY_COM U2PHYDTM1 */
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#define P2C_RG_UART_EN (0x1 << 16)
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#define P2C_RG_VBUSVALID (0x1 << 5)
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#define P2C_RG_SESSEND (0x1 << 4)
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#define P2C_RG_AVALID (0x1 << 2)
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/* U3PHYA PHYA_REG0 */
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#define P3A_RG_U3_VUSB10_ON (1 << 5)
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/* U3PHYA PHYA_REG6 */
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#define P3A_RG_TX_EIDLE_CM (0xf << 28)
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#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
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/* U3PHYA PHYA_REG9 */
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#define P3A_RG_RX_DAC_MUX (0x1f << 1)
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#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
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/* U3PHYA_DA REG0 */
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#define P3A_RG_XTAL_EXT_EN_U3 (0x3 << 10)
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#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
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/* U3PHYD CDR1 */
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#define P3D_RG_CDR_BIR_LTD1 (0x1f << 24)
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#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)
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#define P3D_RG_CDR_BIR_LTD0 (0x1f << 8)
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#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)
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struct sif_u2_phy_com {
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u32 reserved0[5];
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u32 usbphyacr5;
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u32 usbphyacr6;
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u32 u2phyacr3;
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u32 u2phyacr4;
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u32 reserved1[17];
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u32 u2phydtm0;
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u32 u2phydtm1;
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u32 reserved2[36]; /* 0x70 - 0xff */
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};
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check_member(sif_u2_phy_com, u2phydtm0, 0x68);
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struct sif_u3phyd {
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u32 reserved0[23];
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u32 phyd_cdr1;
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u32 reserved1[40];
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};
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struct sif_u3phya {
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u32 phya_reg0;
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u32 reserved0[5];
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u32 phya_reg6;
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u32 reserved1[2];
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u32 phya_reg9;
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u32 reserved2[54];
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};
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struct sif_u3phya_da {
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u32 reg0;
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u32 reserved[63];
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};
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struct ssusb_sif_port {
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struct sif_u2_phy_com u2phy;
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struct sif_u3phyd u3phyd;
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u32 reserved0[64];
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struct sif_u3phya u3phya;
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struct sif_u3phya_da u3phya_da;
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u32 reserved1[64 * 3];
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};
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check_member(ssusb_sif_port, u3phyd, 0x100);
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check_member(ssusb_sif_port, u3phya, 0x300);
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check_member(ssusb_sif_port, u3phya_da, 0x400);
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check_member(ssusb_sif_port, reserved1, 0x500);
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_Static_assert(sizeof(struct ssusb_sif_port) == 0x800, \
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"ssusb_sif_port size is wrong!");
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void setup_usb_host(void);
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#endif
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@ -0,0 +1,170 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <delay.h>
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#include <soc/addressmap.h>
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#include <soc/pll.h>
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#include <soc/usb.h>
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#include <timer.h>
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#define USBTAG "[SSUSB] "
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#define u3p_msg(fmt, arg...) printk(BIOS_INFO, USBTAG fmt, ##arg)
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#define u3p_err(fmt, arg...) printk(BIOS_ERR, USBTAG fmt, ##arg)
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static struct ssusb_ippc_regs *ippc_regs = (void *)(SSUSB_IPPC_BASE);
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static struct ssusb_sif_port *phy_ports = (void *)(SSUSB_SIF_BASE);
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static void phy_index_power_on(int index)
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{
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struct ssusb_sif_port *phy = phy_ports + index;
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if (!index) {
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/* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */
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setbits_le32(&phy->u3phya.phya_reg0, P3A_RG_U3_VUSB10_ON);
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/* power domain iso disable */
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clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_ISO_EN);
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}
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/* switch to USB function. (system register, force ip into usb mode) */
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clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_UART_EN);
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clrbits_le32(&phy->u2phy.u2phydtm1, P2C_RG_UART_EN);
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if (!index)
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clrbits_le32(&phy->u2phy.u2phyacr4, P2C_U2_GPIO_CTR_MSK);
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/* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */
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clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_SUSPENDM |
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P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
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/* DP/DM BC1.1 path Disable */
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clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_BC11_SW_EN);
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/* improve Rx sensitivity */
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clrsetbits_le32(&phy->u2phy.usbphyacr6,
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PA6_RG_U2_SQTH, PA6_RG_U2_SQTH_VAL(2));
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/* OTG Enable */
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setbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_OTG_VBUSCMP_EN);
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clrsetbits_le32(&phy->u3phya_da.reg0,
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P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2));
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clrsetbits_le32(&phy->u3phya.phya_reg9,
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P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4));
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if (!index) {
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/* [mt8173]disable Change 100uA current from SSUSB */
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clrbits_le32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HS_100U_U3_EN);
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}
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clrsetbits_le32(&phy->u3phya.phya_reg6,
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P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe));
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clrsetbits_le32(&phy->u3phyd.phyd_cdr1,
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P3D_RG_CDR_BIR_LTD0, P3D_RG_CDR_BIR_LTD0_VAL(0xc));
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clrsetbits_le32(&phy->u3phyd.phyd_cdr1,
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P3D_RG_CDR_BIR_LTD1, P3D_RG_CDR_BIR_LTD1_VAL(0x3));
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clrsetbits_le32(&phy->u2phy.u2phydtm1,
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P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID);
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/* USB 2.0 slew rate calibration */
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clrsetbits_le32(&phy->u2phy.usbphyacr5,
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PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));
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}
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static void u3phy_power_on(void)
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{
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phy_index_power_on(0);
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phy_index_power_on(1);
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}
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static int check_ip_clk_status(void)
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{
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int u3_port_num;
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u32 check_bits;
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u32 sts1, sts2;
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struct stopwatch sw;
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u3_port_num = CAP_U3_PORT_NUM(read32(&ippc_regs->ip_xhci_cap));
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check_bits = STS1_SYSPLL_STABLE | STS1_REF_RST | STS1_SYS125_RST;
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check_bits = (u3_port_num ? STS1_U3_MAC_RST : 0);
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stopwatch_init_usecs_expire(&sw, 50000);
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do {
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if (stopwatch_expired(&sw)) {
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u3p_err("usb clocks are not stable!!!\n");
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return -1;
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}
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sts1 = read32(&ippc_regs->ip_pw_sts1) & check_bits;
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sts2 = read32(&ippc_regs->ip_pw_sts2) & STS2_U2_MAC_RST;
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} while ((sts1 != check_bits) || !sts2);
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return 0;
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}
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static int u3phy_ports_enable(void)
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{
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int i;
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u32 value;
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int u3_port_num;
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int u2_port_num;
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value = read32(&ippc_regs->ip_xhci_cap);
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u3_port_num = CAP_U3_PORT_NUM(value);
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u2_port_num = CAP_U2_PORT_NUM(value);
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u3p_msg("%s u2p:%d, u3p:%d\n", __func__, u2_port_num, u3_port_num);
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/* power on host ip */
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clrbits_le32(&ippc_regs->ip_pw_ctr1, CTRL1_IP_HOST_PDN);
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/* power on and enable all u3 ports */
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for (i = 0; i < u3_port_num; i++) {
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clrsetbits_le32(&ippc_regs->u3_ctrl_p[i],
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CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS, CTRL_U3_PORT_HOST_SEL);
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}
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/* power on and enable all u2 ports */
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for (i = 0; i < u2_port_num; i++) {
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clrsetbits_le32(&ippc_regs->u2_ctrl_p[i],
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CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS, CTRL_U2_PORT_HOST_SEL);
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}
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return check_ip_clk_status();
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}
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static inline void ssusb_soft_reset(void)
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{
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/* reset whole ip */
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setbits_le32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST);
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clrbits_le32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST);
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}
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void setup_usb_host(void)
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{
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int ret;
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u3p_msg("Setting up USB HOST controller...\n");
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mt_pll_enable_ssusb_clk();
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ssusb_soft_reset();
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ret = u3phy_ports_enable();
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if (ret) {
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u3p_err("%s fail to enable ports\n", __func__);
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return;
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}
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u3phy_power_on();
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u3p_msg("phy power-on done.\n");
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}
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