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mediatek/mt8173: Add usb phy driver 

BRANCH=none
BUG=none
TEST=build pass and test it ok on oak

Change-Id: Ib3d3f420dd576a63d7504dd0949040a3d430c675
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b17b03ed40b562a520185fa243bc4458daed6f23
Original-Change-Id: Ib9346f7913433ca82e8123feaf34fd0d6c071047
Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292687
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13095
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Chunfeng Yun 2015-07-31 17:11:08 +08:00 committed by Patrick Georgi
parent cc248bcce3
commit f764d1458d
3 changed files with 350 additions and 0 deletions
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2
src/soc/mediatek/mt8173/Makefile.inc
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@ -64,6 +64,8 @@ ramstage-y += gpio.c
ramstage-y += wdt.c ramstage-y += wdt.c
ramstage-y += pll.c ramstage-y += pll.c
ramstage-y += usb.c
################################################################################ ################################################################################
# Generate the actual coreboot bootblock code # Generate the actual coreboot bootblock code

178
src/soc/mediatek/mt8173/include/soc/usb.h Normal file
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@ -0,0 +1,178 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SOC_MEDIATEK_MT8173_USB_H
#define SOC_MEDIATEK_MT8173_USB_H
/* ip_pw_ctrl0 */
#define CTRL0_IP_SW_RST (0x1 << 0)
/* ip_pw_ctrl1 */
#define CTRL1_IP_HOST_PDN (0x1 << 0)
/* ip_pw_sts1 */
#define STS1_U3_MAC_RST (0x1 << 16)
#define STS1_SYS125_RST (0x1 << 10)
#define STS1_REF_RST (0x1 << 8)
#define STS1_SYSPLL_STABLE (0x1 << 0)
/* ip_pw_sts2 */
#define STS2_U2_MAC_RST (0x1 << 0)
/* ip_xhci_cap */
#define CAP_U3_PORT_NUM(p) ((p) & 0xff)
#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
/* u3_ctrl_p */
#define CTRL_U3_PORT_HOST_SEL (0x1 << 2)
#define CTRL_U3_PORT_PDN (0x1 << 1)
#define CTRL_U3_PORT_DIS (0x1 << 0)
/* u2_ctrl_p */
#define CTRL_U2_PORT_HOST_SEL (0x1 << 2)
#define CTRL_U2_PORT_PDN (0x1 << 1)
#define CTRL_U2_PORT_DIS (0x1 << 0)
struct ssusb_ippc_regs {
u32 ip_pw_ctr0;
u32 ip_pw_ctr1;
u32 ip_pw_ctr2;
u32 ip_pw_ctr3;
u32 ip_pw_sts1;
u32 ip_pw_sts2;
u32 reserved0[3];
u32 ip_xhci_cap;
u32 reserved1[2];
u64 u3_ctrl_p[4];
u64 u2_ctrl_p[6];
};
/* U2PHY_COM USBPHYACR5 */
#define PA5_RG_U2_HSTX_SRCTRL (0x7 << 12)
#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
#define PA5_RG_U2_HS_100U_U3_EN (0x1 << 11)
/* U2PHY_COM USBPHYACR6 */
#define PA6_RG_U2_ISO_EN (0x1 << 31)
#define PA6_RG_U2_BC11_SW_EN (0x1 << 23)
#define PA6_RG_U2_OTG_VBUSCMP_EN (0x1 << 20)
#define PA6_RG_U2_SQTH (0xf << 0)
#define PA6_RG_U2_SQTH_VAL(x) ((0xf & (x)) << 0)
/* U2PHY_COM U2PHYACR4 */
#define P2C_RG_USB20_GPIO_CTL (0x1 << 9)
#define P2C_USB20_GPIO_MODE (0x1 << 8)
#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
/* U2PHY_COM U2PHYDTM0 */
#define P2C_FORCE_UART_EN (0x1 << 26)
#define P2C_FORCE_DATAIN (0x1 << 23)
#define P2C_FORCE_DM_PULLDOWN (0x1 << 21)
#define P2C_FORCE_DP_PULLDOWN (0x1 << 20)
#define P2C_FORCE_XCVRSEL (0x1 << 19)
#define P2C_FORCE_SUSPENDM (0x1 << 18)
#define P2C_FORCE_TERMSEL (0x1 << 17)
#define P2C_RG_DATAIN (0xf << 10)
#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10)
#define P2C_RG_DMPULLDOWN (0x1 << 7)
#define P2C_RG_DPPULLDOWN (0x1 << 6)
#define P2C_RG_XCVRSEL (0x3 << 4)
#define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4)
#define P2C_RG_SUSPENDM (0x1 << 3)
#define P2C_RG_TERMSEL (0x1 << 2)
#define P2C_DTM0_PART_MASK \
(P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
P2C_RG_TERMSEL)
/* U2PHY_COM U2PHYDTM1 */
#define P2C_RG_UART_EN (0x1 << 16)
#define P2C_RG_VBUSVALID (0x1 << 5)
#define P2C_RG_SESSEND (0x1 << 4)
#define P2C_RG_AVALID (0x1 << 2)
/* U3PHYA PHYA_REG0 */
#define P3A_RG_U3_VUSB10_ON (1 << 5)
/* U3PHYA PHYA_REG6 */
#define P3A_RG_TX_EIDLE_CM (0xf << 28)
#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
/* U3PHYA PHYA_REG9 */
#define P3A_RG_RX_DAC_MUX (0x1f << 1)
#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
/* U3PHYA_DA REG0 */
#define P3A_RG_XTAL_EXT_EN_U3 (0x3 << 10)
#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
/* U3PHYD CDR1 */
#define P3D_RG_CDR_BIR_LTD1 (0x1f << 24)
#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)
#define P3D_RG_CDR_BIR_LTD0 (0x1f << 8)
#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)
struct sif_u2_phy_com {
u32 reserved0[5];
u32 usbphyacr5;
u32 usbphyacr6;
u32 u2phyacr3;
u32 u2phyacr4;
u32 reserved1[17];
u32 u2phydtm0;
u32 u2phydtm1;
u32 reserved2[36]; /* 0x70 - 0xff */
};
check_member(sif_u2_phy_com, u2phydtm0, 0x68);
struct sif_u3phyd {
u32 reserved0[23];
u32 phyd_cdr1;
u32 reserved1[40];
};
struct sif_u3phya {
u32 phya_reg0;
u32 reserved0[5];
u32 phya_reg6;
u32 reserved1[2];
u32 phya_reg9;
u32 reserved2[54];
};
struct sif_u3phya_da {
u32 reg0;
u32 reserved[63];
};
struct ssusb_sif_port {
struct sif_u2_phy_com u2phy;
struct sif_u3phyd u3phyd;
u32 reserved0[64];
struct sif_u3phya u3phya;
struct sif_u3phya_da u3phya_da;
u32 reserved1[64 * 3];
};
check_member(ssusb_sif_port, u3phyd, 0x100);
check_member(ssusb_sif_port, u3phya, 0x300);
check_member(ssusb_sif_port, u3phya_da, 0x400);
check_member(ssusb_sif_port, reserved1, 0x500);
_Static_assert(sizeof(struct ssusb_sif_port) == 0x800, \
"ssusb_sif_port size is wrong!");
void setup_usb_host(void);
#endif

170
src/soc/mediatek/mt8173/usb.c Normal file
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@ -0,0 +1,170 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <console/console.h>
#include <delay.h>
#include <soc/addressmap.h>
#include <soc/pll.h>
#include <soc/usb.h>
#include <timer.h>
#define USBTAG "[SSUSB] "
#define u3p_msg(fmt, arg...) printk(BIOS_INFO, USBTAG fmt, ##arg)
#define u3p_err(fmt, arg...) printk(BIOS_ERR, USBTAG fmt, ##arg)
static struct ssusb_ippc_regs *ippc_regs = (void *)(SSUSB_IPPC_BASE);
static struct ssusb_sif_port *phy_ports = (void *)(SSUSB_SIF_BASE);
static void phy_index_power_on(int index)
{
struct ssusb_sif_port *phy = phy_ports + index;
if (!index) {
/* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */
setbits_le32(&phy->u3phya.phya_reg0, P3A_RG_U3_VUSB10_ON);
/* power domain iso disable */
clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_ISO_EN);
}
/* switch to USB function. (system register, force ip into usb mode) */
clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_UART_EN);
clrbits_le32(&phy->u2phy.u2phydtm1, P2C_RG_UART_EN);
if (!index)
clrbits_le32(&phy->u2phy.u2phyacr4, P2C_U2_GPIO_CTR_MSK);
/* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */
clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_SUSPENDM |
P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
/* DP/DM BC1.1 path Disable */
clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_BC11_SW_EN);
/* improve Rx sensitivity */
clrsetbits_le32(&phy->u2phy.usbphyacr6,
PA6_RG_U2_SQTH, PA6_RG_U2_SQTH_VAL(2));
/* OTG Enable */
setbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_OTG_VBUSCMP_EN);
clrsetbits_le32(&phy->u3phya_da.reg0,
P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2));
clrsetbits_le32(&phy->u3phya.phya_reg9,
P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4));
if (!index) {
/* [mt8173]disable Change 100uA current from SSUSB */
clrbits_le32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HS_100U_U3_EN);
}
clrsetbits_le32(&phy->u3phya.phya_reg6,
P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe));
clrsetbits_le32(&phy->u3phyd.phyd_cdr1,
P3D_RG_CDR_BIR_LTD0, P3D_RG_CDR_BIR_LTD0_VAL(0xc));
clrsetbits_le32(&phy->u3phyd.phyd_cdr1,
P3D_RG_CDR_BIR_LTD1, P3D_RG_CDR_BIR_LTD1_VAL(0x3));
clrsetbits_le32(&phy->u2phy.u2phydtm1,
P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID);
/* USB 2.0 slew rate calibration */
clrsetbits_le32(&phy->u2phy.usbphyacr5,
PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));
}
static void u3phy_power_on(void)
{
phy_index_power_on(0);
phy_index_power_on(1);
}
static int check_ip_clk_status(void)
{
int u3_port_num;
u32 check_bits;
u32 sts1, sts2;
struct stopwatch sw;
u3_port_num = CAP_U3_PORT_NUM(read32(&ippc_regs->ip_xhci_cap));
check_bits = STS1_SYSPLL_STABLE | STS1_REF_RST | STS1_SYS125_RST;
check_bits = (u3_port_num ? STS1_U3_MAC_RST : 0);
stopwatch_init_usecs_expire(&sw, 50000);
do {
if (stopwatch_expired(&sw)) {
u3p_err("usb clocks are not stable!!!\n");
return -1;
}
sts1 = read32(&ippc_regs->ip_pw_sts1) & check_bits;
sts2 = read32(&ippc_regs->ip_pw_sts2) & STS2_U2_MAC_RST;
} while ((sts1 != check_bits) || !sts2);
return 0;
}
static int u3phy_ports_enable(void)
{
int i;
u32 value;
int u3_port_num;
int u2_port_num;
value = read32(&ippc_regs->ip_xhci_cap);
u3_port_num = CAP_U3_PORT_NUM(value);
u2_port_num = CAP_U2_PORT_NUM(value);
u3p_msg("%s u2p:%d, u3p:%d\n", __func__, u2_port_num, u3_port_num);
/* power on host ip */
clrbits_le32(&ippc_regs->ip_pw_ctr1, CTRL1_IP_HOST_PDN);
/* power on and enable all u3 ports */
for (i = 0; i < u3_port_num; i++) {
clrsetbits_le32(&ippc_regs->u3_ctrl_p[i],
CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS, CTRL_U3_PORT_HOST_SEL);
}
/* power on and enable all u2 ports */
for (i = 0; i < u2_port_num; i++) {
clrsetbits_le32(&ippc_regs->u2_ctrl_p[i],
CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS, CTRL_U2_PORT_HOST_SEL);
}
return check_ip_clk_status();
}
static inline void ssusb_soft_reset(void)
{
/* reset whole ip */
setbits_le32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST);
clrbits_le32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST);
}
void setup_usb_host(void)
{
int ret;
u3p_msg("Setting up USB HOST controller...\n");
mt_pll_enable_ssusb_clk();
ssusb_soft_reset();
ret = u3phy_ports_enable();
if (ret) {
u3p_err("%s fail to enable ports\n", __func__);
return;
}
u3phy_power_on();
u3p_msg("phy power-on done.\n");
}