code reformat, removed unused code
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -161,13 +161,16 @@ static void main(void)
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enable_lapic();
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init_timer();
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if (cpu_init_detected()) {
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asm("jmp __cpu_reset");
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}
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distinguish_cpu_resets();
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if (!boot_cpu()) {
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stop_this_cpu();
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}
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pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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@ -3,268 +3,22 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <cpu/p6/msr.h>
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#include <arch/io.h>
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#include <device/chip.h>
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#include "../../../northbridge/amd/amdk8/northbridge.h"
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#include "chip.h"
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#include "pc80/mc146818rtc.h"
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unsigned long initial_apicid[CONFIG_MAX_CPUS] =
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{
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0, 1,
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};
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#define SMBGSTATUS 0xe0
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#define SMBGCTL 0xe2
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#define SMBHSTADDR 0xe4
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#define SMBHSTDAT 0xe6
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#define SMBHSTCMD 0xe8
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#define SMBHSTFIFO 0xe9
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#define SMBUS_TIMEOUT (100*1000*10)
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static inline void smbus_delay(void)
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{
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outb(0x80, 0x80);
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}
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static int smbus_wait_until_ready(unsigned smbus_io_base)
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{
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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do {
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unsigned short val;
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smbus_delay();
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val = inw(smbus_io_base + SMBGSTATUS);
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if ((val & 0x800) == 0) {
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break;
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}
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if(loops == (SMBUS_TIMEOUT / 2)) {
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outw(inw(smbus_io_base + SMBGSTATUS),
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smbus_io_base + SMBGSTATUS);
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}
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} while(--loops);
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return loops?0:-2;
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}
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static int smbus_wait_until_done(unsigned smbus_io_base)
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{
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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do {
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unsigned short val;
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smbus_delay();
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val = inw(smbus_io_base + SMBGSTATUS);
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if (((val & 0x8) == 0) | ((val & 0x437) != 0)) {
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break;
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}
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} while(--loops);
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return loops?0:-3;
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}
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static int smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned value)
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{
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unsigned char global_status_register;
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if (smbus_wait_until_ready(smbus_io_base) < 0) {
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return -2;
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}
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/* setup transaction */
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/* disable interrupts */
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outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
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/* set the device I'm talking too */
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outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
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/* set the command/address... */
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outb(0, smbus_io_base + SMBHSTCMD);
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/* set up for a send byte */
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outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x1), smbus_io_base + SMBGCTL);
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/* clear any lingering errors, so the transaction will run */
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/* Do I need to write the bits to a 1 to clear an error? */
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outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
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/* set the data word...*/
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outw(value, smbus_io_base + SMBHSTDAT);
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/* start the command */
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outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
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/* poll for transaction completion */
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if (smbus_wait_until_done(smbus_io_base) < 0) {
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return -3;
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}
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global_status_register = inw(smbus_io_base + SMBGSTATUS);
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if (global_status_register != (1 << 4)) {
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return -1;
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}
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return 0;
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}
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static int smbus_recv_byte(unsigned smbus_io_base, unsigned device)
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{
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unsigned char global_status_register;
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unsigned char byte;
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if (smbus_wait_until_ready(smbus_io_base) < 0) {
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return -2;
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}
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/* setup transaction */
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/* disable interrupts */
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outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
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/* set the device I'm talking too */
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outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
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/* set the command/address... */
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outb(0, smbus_io_base + SMBHSTCMD);
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/* set up for a send byte */
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outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x1), smbus_io_base + SMBGCTL);
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/* clear any lingering errors, so the transaction will run */
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/* Do I need to write the bits to a 1 to clear an error? */
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outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
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/* set the data word...*/
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outw(0, smbus_io_base + SMBHSTDAT);
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/* start the command */
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outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
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/* poll for transaction completion */
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if (smbus_wait_until_done(smbus_io_base) < 0) {
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return -3;
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}
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global_status_register = inw(smbus_io_base + SMBGSTATUS);
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/* read results of transaction */
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byte = inw(smbus_io_base + SMBHSTDAT) & 0xff;
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if (global_status_register != (1 << 4)) {
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return -1;
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}
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return byte;
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}
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#if 0
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static int smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
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{
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unsigned char global_status_register;
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unsigned char byte;
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if (smbus_wait_until_ready(smbus_io_base) < 0) {
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return -2;
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}
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/* setup transaction */
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/* disable interrupts */
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outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
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/* set the device I'm talking too */
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outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
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/* set the command/address... */
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outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
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/* set up for a byte data read */
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outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x2), smbus_io_base + SMBGCTL);
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/* clear any lingering errors, so the transaction will run */
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/* Do I need to write the bits to a 1 to clear an error? */
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outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
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/* clear the data word...*/
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outw(0, smbus_io_base + SMBHSTDAT);
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/* start the command */
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outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
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/* poll for transaction completion */
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if (smbus_wait_until_done(smbus_io_base) < 0) {
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return -3;
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}
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global_status_register = inw(smbus_io_base + SMBGSTATUS);
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/* read results of transaction */
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byte = inw(smbus_io_base + SMBHSTDAT) & 0xff;
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if (global_status_register != (1 << 4)) {
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return -1;
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}
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return byte;
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}
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static int smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val)
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{
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if (smbus_wait_until_ready(smbus_io_base) < 0) {
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return -2;
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}
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/* setup transaction */
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/* disable interrupts */
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outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)),
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smbus_io_base + SMBGCTL);
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/* set the device I'm talking too */
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outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
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outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
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/* set up for a byte data write */ /* FIXME */
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outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x1), smbus_io_base + SMBGCTL);
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/* clear any lingering errors, so the transaction will run */
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/* Do I need to write the bits to a 1 to clear an error? */
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outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
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/* clear the data word...*/
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outw(val, smbus_io_base + SMBHSTDAT);
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/* start the command */
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outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
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/* poll for transaction completion */
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if (smbus_wait_until_done(smbus_io_base) < 0) {
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return -3;
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}
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return 0;
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}
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#endif
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#define SMBUS_MUX 0x70
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static void mainboard_init(device_t dev)
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{
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/* Set the mux to see the temperature sensors */
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dev = dev_find_device(0x1022, 0x746b, 0);
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if (dev) {
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unsigned smbus_io_base;
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unsigned device;
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int result;
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int mux_setting;
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device = SMBUS_MUX;
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mux_setting = 1;
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smbus_io_base = pci_read_config32(dev, 0x58) & ~1;;
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result = smbus_send_byte(smbus_io_base, device, mux_setting);
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if ((result < 0) ||
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(smbus_recv_byte(smbus_io_base, device) != mux_setting)) {
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printk_err("SMBUS mux would not set to %d\n", mux_setting);
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}
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}
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else {
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printk_err("SMBUS_controller not found\n");
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}
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}
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static struct device_operations mainboard_operations = {
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.read_resources = root_dev_read_resources,
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.set_resources = root_dev_set_resources,
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.enable_resources = enable_childrens_resources,
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.init = mainboard_init,
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.init = 0,
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.scan_bus = amdk8_scan_root_bus,
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.enable = 0,
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};
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@ -289,4 +43,3 @@ struct chip_control mainboard_ibm_e325_control = {
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.enumerate = enumerate,
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.name = "IBM E325 mainboard ",
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};
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