[REMOVAL] tyan/s2735
As announced in http://permalink.gmane.org/gmane.linux.bios/81918 I am removing all boards older than 10 years from the tree. Change-Id: I460208c18964857be73d9a4449ecfd872ccad98a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12374 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Stefan Reinauer
parent
63d5088bb6
commit
f76de841f1
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@ -1,41 +0,0 @@
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if BOARD_TYAN_S2735
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_INTEL_SOCKET_MPGA604
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select NORTHBRIDGE_INTEL_E7501
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select SOUTHBRIDGE_INTEL_I82870
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select SOUTHBRIDGE_INTEL_I82801EX
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select SUPERIO_WINBOND_W83627HF
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select UDELAY_TSC
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select HAVE_OPTION_TABLE
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select USE_WATCHDOG_ON_BOOT
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select BOARD_ROMSIZE_KB_512
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config MAINBOARD_DIR
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string
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default tyan/s2735
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config DCACHE_RAM_BASE
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hex
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default 0xcf000
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config DCACHE_RAM_SIZE
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hex
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default 0x1000
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config MAINBOARD_PART_NUMBER
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string
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default "S2735"
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config IRQ_SLOT_COUNT
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int
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default 15
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config MAX_CPUS
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int
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default 4
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endif # BOARD_TYAN_S2735
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@ -1,2 +0,0 @@
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config BOARD_TYAN_S2735
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bool "S2735 (Tiger i7501R)"
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@ -1,4 +0,0 @@
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Board name: Tiger i7501R (S2735)
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Category: server
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Board URL: http://www.tyan.com/archive/products/html/tigeri7501r.html
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Release year: 2003
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@ -1,46 +0,0 @@
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entries
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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395 1 e 2 hyper_threading
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396 1 e 1 thermal_monitoring
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397 1 e 1 remap_memory_high
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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#440 4 e 9 slow_cpu
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444 1 e 1 nmi
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456 1 e 1 ECC_memory
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728 256 h 0 user_data
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984 16 h 0 check_sum
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# Reserve the extended AMD configuration registers
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1000 24 r 0 amd_reserved
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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checksums
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checksum 392 983 984
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@ -1,85 +0,0 @@
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chip northbridge/intel/e7501
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device domain 0 on
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subsystemid 0x10f1 0x2735 inherit
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 2.0 on
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chip southbridge/intel/i82870
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device pci 1c.0 on end
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device pci 1d.0 on
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device pci 1.0 on end # intel lan
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device pci 1.1 on end
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end
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device pci 1e.0 on end
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device pci 1f.0 on end
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end
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end
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device pci 6.0 on end
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chip southbridge/intel/i82801ex
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device pci 1d.0 on end
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device pci 1d.1 on end
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device pci 1d.2 on end
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device pci 1d.3 on end
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device pci 1d.7 on end
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device pci 1e.0 on
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device pci 1.0 on end # intel lan 10/100
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device pci 2.0 on end # ati
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end
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device pci 1f.0 on
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chip superio/winbond/w83627hf
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.6 off # CIR
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io 0x60 = 0x100
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end
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device pnp 2e.7 off # GAME_MIDI_GIPO1
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io 0x60 = 0x220
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io 0x62 = 0x300
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irq 0x70 = 9
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end
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device pnp 2e.8 off end # GPIO2
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device pnp 2e.9 off end # GPIO3
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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irq 0x70 = 5
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end
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end
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end
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device pci 1f.1 off end
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device pci 1f.2 on end
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device pci 1f.3 on end
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device pci 1f.5 off end
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device pci 1f.6 off end
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end # SB
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end # PCI domain
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device cpu_cluster 0 on
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chip cpu/intel/socket_mPGA604
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device lapic 0 on end
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end
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chip cpu/intel/socket_mPGA604
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device lapic 6 on end
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end
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end
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end
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@ -1,38 +0,0 @@
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#include <arch/pirq_routing.h>
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static const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
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0x00, /* Where the interrupt router lies (bus) */
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(0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
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0, /* IRQs devoted exclusively to PCI usage */
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0x8086, /* Vendor */
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0x24d0, /* Device */
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0, /* Miniport data */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x9a, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x04,(0x08<<3)|0x0, {{0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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{0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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{0x00,(0x1d<<3)|0x0, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x0, 0x0},
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{0x04,(0x03<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x60, 0xdcf8}, {0x61, 0x0dcf8}}, 0x3, 0x0},
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{0x04,(0x02<<3)|0x0, {{0x62, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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{0x03,(0x1f<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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{0x02,(0x1f<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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{0x03,(0x03<<3)|0x0, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0x0dcf8}}, 0x1, 0x0},
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{0x03,(0x06<<3)|0x0, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0x0dcf8}}, 0x2, 0x0},
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{0x02,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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{0x02,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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{0x04,(0x01<<3)|0x0, {{0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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{0x04,(0x04<<3)|0x0, {{0x63, 0xdcf8}, {0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0x0dcf8}}, 0x4, 0x0},
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{0x03,(0x04<<3)|0x0, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
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{0x03,(0x05<<3)|0x0, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0x0dcf8}}, 0x6, 0x0},
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr, &intel_irq_routing_table);
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}
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@ -1,132 +0,0 @@
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#include <console/console.h>
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#include <arch/smp/mpspec.h>
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#include <arch/ioapic.h>
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#include <device/pci.h>
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#include <string.h>
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#include <stdint.h>
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int isa_bus;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LOCAL_APIC_ADDR);
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smp_write_processors(mc);
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mptable_write_buses(mc, NULL, &isa_bus);
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/*I/O APICs: APIC ID Version State Address*/
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smp_write_ioapic(mc, 8, 0x20, VIO_APIC_VADDR);
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{
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device_t dev;
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struct resource *res;
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dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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smp_write_ioapic(mc, 0x09, 0x20,
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res2mmio(res, 0, 0));
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}
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}
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dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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smp_write_ioapic(mc, 0x0a, 0x20,
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res2mmio(res, 0, 0));
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}
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}
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}
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mptable_add_isa_interrupts(mc, isa_bus, 0x8, 0);
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/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
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*/
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//USB
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7c, 0x8, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x8, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x8, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x8, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x8, 0x17);
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//onboard ati
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x8, 0x8, 0x12);
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//onboard intel 82551 10/100
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x4, 0x8, 0x11);
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// onboard Intel 82547 1000
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x4, 0xa, 0x0);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x5, 0xa, 0x1);
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//Slot 4
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|0, 0x8, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|1, 0x8, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|2, 0x8, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|3, 0x8, 0x11);
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//Slot 3
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|0, 0x8, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|1, 0x8, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|2, 0x8, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|3, 0x8, 0x12);
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//Slot 1
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|0, 0x9, 0x0);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|1, 0x9, 0x1);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|2, 0x9, 0x2);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|3, 0x9, 0x3);
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//Slot 2
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|0, 0x9, 0x4);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|1, 0x9, 0x5);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|2, 0x9, 0x6);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|3, 0x9, 0x7);
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/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
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mptable_lintsrc(mc, 0x0);
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/*
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MP Config Extended Table Entries:
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--
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System Address Space
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bus ID: 0 address type: I/O address
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address base: 0x9000
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address range: 0x6000
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--
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System Address Space
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bus ID: 0 address type: I/O address
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address base: 0x0
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address range: 0x100
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--
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System Address Space
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bus ID: 0 address type: memory address
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address base: 0xa0000
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address range: 0x20000
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--
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System Address Space
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bus ID: 0 address type: memory address
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address base: 0xfc700000
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address range: 0x2500000
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--
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System Address Space
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bus ID: 0 address type: prefetch address
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address base: 0xff600000
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address range: 0x500000
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--
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Bus Heirarchy
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bus ID: 5 bus info: 0x01 parent bus ID: 0--
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Compatibility Bus Address
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bus ID: 0 address modifier: add
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predefined range: 0x00000000--
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Compatibility Bus Address
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bus ID: 0 address modifier: add
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predefined range: 0x00000001 // There is no extension information...
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*/
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/* Compute the checksums */
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return mptable_finalize(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr, 0);
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return (unsigned long)smp_write_config_table(v);
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}
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@ -1,76 +0,0 @@
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#include <stdint.h>
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#include <string.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <cpu/x86/lapic.h>
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#include <pc80/mc146818rtc.h>
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#include <console/console.h>
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#include <lib.h>
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#include <spd.h>
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#include "southbridge/intel/i82801ex/early_smbus.c"
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#include <northbridge/intel/e7501/raminit.h>
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#include "northbridge/intel/e7501/debug.c"
|
||||
#include <superio/winbond/common/winbond.h>
|
||||
#include <superio/winbond/w83627hf/w83627hf.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
|
||||
// FIXME: There's another hard_reset() in reset.c. Why?
|
||||
static void hard_reset(void)
|
||||
{
|
||||
/* full reset */
|
||||
outb(0x0a, 0x0cf9);
|
||||
outb(0x0e, 0x0cf9);
|
||||
}
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/intel/e7501/raminit.c"
|
||||
#include "northbridge/intel/e7501/reset_test.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
|
||||
#include <cpu/intel/romstage.h>
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller memctrl[] = {
|
||||
{
|
||||
.d0 = PCI_DEV(0, 0, 0),
|
||||
.d0f1 = PCI_DEV(0, 0, 1),
|
||||
.channel0 = { DIMM0, DIMM1, DIMM2, 0 },
|
||||
.channel1 = { DIMM4, DIMM5, DIMM6, 0 },
|
||||
},
|
||||
};
|
||||
|
||||
if (bist == 0)
|
||||
enable_lapic();
|
||||
|
||||
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
if (bios_reset_detected())
|
||||
hard_reset();
|
||||
|
||||
enable_smbus();
|
||||
#if 0
|
||||
dump_spd_registers(&memctrl[0]);
|
||||
dump_smbus_registers();
|
||||
#endif
|
||||
|
||||
sdram_initialize(1, memctrl);
|
||||
|
||||
#if 0
|
||||
dump_pci_devices();
|
||||
#endif
|
||||
|
||||
#if 1
|
||||
dump_pci_device(PCI_DEV(0, 0, 0));
|
||||
#endif
|
||||
}
|
||||
Loading…
Reference in New Issue