pcengines/apu2: Switch away from BINARYPI_LEGACY_WRAPPER
Adopting the mainboard code to use hooks from state_machine.h. No post codes are changed, except for those which were explicitly sent in mainboard/romstage.c. Boot time is reduced by more than 7%, from 5.029s to 4.657s (coreboot timestamps, measured for loglevel 7). POSTCAR_STAGE is required since coreboot 4.11 release. TEST=boot PC Engines apu2 and launch Debian Linux with 4.14.50 kernel Change-Id: Iff3dbe68ac17eb2947ff40b9769c6650255656cf Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Krystian Hebel
Kyösti Mälkki
parent
6a23352515
commit
f77f2c79c2
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@ -17,6 +17,7 @@
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#include <console/console.h>
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#include <spd_bin.h>
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#include <northbridge/amd/agesa/BiosCallOuts.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <FchPlatform.h>
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#include <stdlib.h>
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@ -24,7 +25,6 @@
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#include "imc.h"
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#include "hudson.h"
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static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
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static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
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const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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@ -35,8 +35,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
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{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
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{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
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{AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }
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};
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const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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@ -57,75 +56,67 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
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FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 1 enable, 0 disable TSI Auto Polling */
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}
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/**
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* Fch Oem setting callback
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*
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* Configure platform specific Hudson device,
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* such Azalia, SATA, IMC etc.
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*/
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static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
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void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams)
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{
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AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr;
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if (StdHeader->Func == AMD_INIT_RESET) {
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FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
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//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
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FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
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FchParams->FchReset.SataEnable = hudson_sata_enable();
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FchParams->FchReset.IdeEnable = hudson_ide_enable();
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FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
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FchParams->FchReset.Xhci1Enable = FALSE;
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} else if (StdHeader->Func == AMD_INIT_ENV) {
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FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
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printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
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//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
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FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
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FchParams->FchReset.SataEnable = hudson_sata_enable();
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FchParams->FchReset.IdeEnable = hudson_ide_enable();
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FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
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FchParams->FchReset.Xhci1Enable = FALSE;
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printk(BIOS_DEBUG, "Done\n");
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}
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void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams)
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{
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printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
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FchParams->Azalia.AzaliaEnable = AzDisable;
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FchParams->Azalia.AzaliaEnable = AzDisable;
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/* Fan Control */
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oem_fan_control(FchParams);
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/* Fan Control */
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oem_fan_control(FchParams);
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/* XHCI configuration */
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FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
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FchParams->Usb.Xhci1Enable = FALSE;
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/* XHCI configuration */
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FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
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FchParams->Usb.Xhci1Enable = FALSE;
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/* EHCI configuration */
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FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE);
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/* EHCI configuration */
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FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE);
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if (CONFIG(BOARD_PCENGINES_APU2)) {
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// Disable EHCI 0 (port 0 to 3)
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FchParams->Usb.Ehci1Enable = FALSE;
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} else {
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// Enable EHCI 0 (port 0 to 3)
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FchParams->Usb.Ehci1Enable = TRUE;
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}
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if (CONFIG(BOARD_PCENGINES_APU2)) {
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// Disable EHCI 0 (port 0 to 3)
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FchParams->Usb.Ehci1Enable = FALSE;
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} else {
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// Enable EHCI 0 (port 0 to 3)
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FchParams->Usb.Ehci1Enable = TRUE;
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}
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// Enable EHCI 1 (port 4 to 7)
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// port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
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FchParams->Usb.Ehci2Enable = TRUE;
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// Enable EHCI 1 (port 4 to 7)
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// port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
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FchParams->Usb.Ehci2Enable = TRUE;
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/* sata configuration */
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FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP
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FchParams->Sata.SataDevSlpPort1 = 0;
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/* sata configuration */
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// Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP
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FchParams->Sata.SataDevSlpPort0 = 0;
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FchParams->Sata.SataDevSlpPort1 = 0;
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FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
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switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
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case SataRaid:
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case SataAhci:
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case SataAhci7804:
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case SataLegacyIde:
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FchParams->Sata.SataIdeMode = FALSE;
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break;
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case SataIde2Ahci:
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case SataIde2Ahci7804:
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default: /* SataNativeIde */
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FchParams->Sata.SataIdeMode = TRUE;
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break;
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}
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FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
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switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
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case SataRaid:
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case SataAhci:
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case SataAhci7804:
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case SataLegacyIde:
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FchParams->Sata.SataIdeMode = FALSE;
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break;
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case SataIde2Ahci:
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case SataIde2Ahci7804:
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default: /* SataNativeIde */
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FchParams->Sata.SataIdeMode = TRUE;
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break;
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}
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printk(BIOS_DEBUG, "Done\n");
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return AGESA_SUCCESS;
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}
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static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
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@ -20,7 +20,6 @@ if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BINARYPI_LEGACY_WRAPPER
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select CPU_AMD_PI_00730F01
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select NORTHBRIDGE_AMD_PI_00730F01
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select SOUTHBRIDGE_AMD_PI_AVALON
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@ -14,7 +14,7 @@
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*/
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#include <AGESA.h>
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#include <northbridge/amd/pi/agesawrapper.h>
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#include <northbridge/amd/agesa/state_machine.h>
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static const PCIe_PORT_DESCRIPTOR PortList[] = {
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@ -76,25 +76,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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.DdiLinkList = NULL,
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};
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/*---------------------------------------------------------------------------------------*/
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/**
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* OemCustomizeInitEarly
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*
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* Description:
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* This stub function will call the host environment through the binary block
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* interface (call-out port) to provide a user hook opportunity
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*
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* Parameters:
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* @param[in] *InitEarly
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*
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* @retval VOID
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*
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**/
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/*---------------------------------------------------------------------------------------*/
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VOID
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OemCustomizeInitEarly (
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IN OUT AMD_EARLY_PARAMS *InitEarly
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)
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void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
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{
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InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
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InitEarly->PlatformConfig.CStateMode = CStateModeC6;
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@ -21,11 +21,8 @@
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#include <arch/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <timestamp.h>
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#include <cpu/amd/car.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <northbridge/amd/pi/agesawrapper.h>
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#include <northbridge/amd/pi/agesawrapper_call.h>
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#include <cpu/x86/bist.h>
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#include <southbridge/amd/pi/hudson/hudson.h>
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#include <superio/nuvoton/common/nuvoton.h>
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@ -40,9 +37,11 @@
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static void early_lpc_init(void);
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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void board_BeforeAgesa(struct sysinfo *cb)
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{
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u32 val;
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pci_devfn_t dev;
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u32 data;
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/*
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* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
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@ -52,85 +51,39 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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* the SoC BKDGs. Without this setting, there is no serial
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* output.
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*/
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outb(0xD2, 0xcd6);
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outb(0xd2, 0xcd6);
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outb(0x00, 0xcd7);
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hudson_lpc_port80();
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if (!cpu_init_detectedx && boot_cpu()) {
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pci_devfn_t dev;
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u32 data;
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post_code(0x30);
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early_lpc_init();
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timestamp_init(timestamp_get());
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timestamp_add_now(TS_START_ROMSTAGE);
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hudson_clk_output_48Mhz();
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post_code(0x31);
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post_code(0x30);
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early_lpc_init();
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dev = PCI_DEV(0, 0x14, 3);
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data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
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/* enable 0x2e/0x4e IO decoding before configuring SuperIO */
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pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
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hudson_clk_output_48Mhz();
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post_code(0x31);
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/* COM2 on apu5 is reserved so only COM1 should be supported */
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if ((CONFIG_UART_FOR_CONSOLE == 1) &&
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!CONFIG(BOARD_PCENGINES_APU5))
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nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
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else if (CONFIG_UART_FOR_CONSOLE == 0)
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nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
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dev = PCI_DEV(0, 0x14, 3);
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data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
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/* enable 0x2e/0x4e IO decoding before configuring SuperIO */
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pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
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/* COM2 on apu5 is reserved so only COM1 should be supported */
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if ((CONFIG_UART_FOR_CONSOLE == 1) &&
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!CONFIG(BOARD_PCENGINES_APU5))
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nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
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else if (CONFIG_UART_FOR_CONSOLE == 0)
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nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
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console_init();
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}
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/* Halt if there was a built in self test failure */
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post_code(0x34);
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report_bist_failure(bist);
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/* Load MPB */
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val = cpuid_eax(1);
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printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
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printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
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post_code(0x37);
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AGESAWRAPPER(amdinitreset);
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post_code(0x38);
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printk(BIOS_DEBUG, "Got past avalon_early_setup\n");
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post_code(0x39);
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AGESAWRAPPER(amdinitearly);
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/* Disable SVI2 controller to wait for command completion */
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val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C);
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if (val & (1 << 30)) {
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printk(BIOS_DEBUG, "SVI2 Wait completion disabled\n");
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} else {
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printk(BIOS_DEBUG, "Disabling SVI2 Wait completion\n");
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if (!(val & (1 << 30))) {
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val |= (1 << 30);
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pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val);
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}
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timestamp_add_now(TS_BEFORE_INITRAM);
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post_code(0x40);
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AGESAWRAPPER(amdinitpost);
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/* FIXME: Detect if TSC frequency changed during raminit? */
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timestamp_rescale_table(1, 4);
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timestamp_add_now(TS_AFTER_INITRAM);
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}
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void agesa_postcar(struct sysinfo *cb)
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{
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//PspMboxBiosCmdDramInfo();
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post_code(0x41);
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AGESAWRAPPER(amdinitenv);
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outb(0xEA, 0xCD6);
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/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
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outb(0xea, 0xcd6);
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outb(0x1, 0xcd7);
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}
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