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pcengines/apu2: Switch away from BINARYPI_LEGACY_WRAPPER 

Adopting the mainboard code to use hooks from state_machine.h.

No post codes are changed, except for those which were explicitly sent in
mainboard/romstage.c. Boot time is reduced by more than 7%, from 5.029s to
4.657s (coreboot timestamps, measured for loglevel 7).

POSTCAR_STAGE is required since coreboot 4.11 release.

TEST=boot PC Engines apu2 and launch Debian Linux with 4.14.50 kernel

Change-Id: Iff3dbe68ac17eb2947ff40b9769c6650255656cf
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Krystian Hebel 2019-04-19 17:59:38 +02:00 committed by Kyösti Mälkki
parent 6a23352515
commit f77f2c79c2
4 changed files with 74 additions and 149 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

111
src/mainboard/pcengines/apu2/BiosCallOuts.c
View File

@ -17,6 +17,7 @@
#include <console/console.h> #include <console/console.h>
#include <spd_bin.h> #include <spd_bin.h>
#include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <FchPlatform.h> #include <FchPlatform.h>
#include <stdlib.h> #include <stdlib.h>
@ -24,7 +25,6 @@
#include "imc.h" #include "imc.h"
#include "hudson.h" #include "hudson.h"
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
const BIOS_CALLOUT_STRUCT BiosCallouts[] = const BIOS_CALLOUT_STRUCT BiosCallouts[] =
@ -35,8 +35,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }
{AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }
}; };
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
@ -57,75 +56,67 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 1 enable, 0 disable TSI Auto Polling */ FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 1 enable, 0 disable TSI Auto Polling */
} }
/** void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams)
* Fch Oem setting callback
*
* Configure platform specific Hudson device,
* such Azalia, SATA, IMC etc.
*/
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
{ {
AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
if (StdHeader->Func == AMD_INIT_RESET) { //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); FchParams->FchReset.SataEnable = hudson_sata_enable();
//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ FchParams->FchReset.IdeEnable = hudson_ide_enable();
FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.Xhci1Enable = FALSE;
FchParams->FchReset.IdeEnable = hudson_ide_enable(); printk(BIOS_DEBUG, "Done\n");
FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); }
FchParams->FchReset.Xhci1Enable = FALSE;
} else if (StdHeader->Func == AMD_INIT_ENV) { void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams)
FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData; {
printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
FchParams->Azalia.AzaliaEnable = AzDisable; FchParams->Azalia.AzaliaEnable = AzDisable;
/* Fan Control */ /* Fan Control */
oem_fan_control(FchParams); oem_fan_control(FchParams);
/* XHCI configuration */ /* XHCI configuration */
FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchParams->Usb.Xhci1Enable = FALSE; FchParams->Usb.Xhci1Enable = FALSE;
/* EHCI configuration */ /* EHCI configuration */
FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE); FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE);
if (CONFIG(BOARD_PCENGINES_APU2)) { if (CONFIG(BOARD_PCENGINES_APU2)) {
// Disable EHCI 0 (port 0 to 3) // Disable EHCI 0 (port 0 to 3)
FchParams->Usb.Ehci1Enable = FALSE; FchParams->Usb.Ehci1Enable = FALSE;
} else { } else {
// Enable EHCI 0 (port 0 to 3) // Enable EHCI 0 (port 0 to 3)
FchParams->Usb.Ehci1Enable = TRUE; FchParams->Usb.Ehci1Enable = TRUE;
} }
// Enable EHCI 1 (port 4 to 7) // Enable EHCI 1 (port 4 to 7)
// port 4 and 5 to EHCI header port 6 and 7 to PCIe slot. // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
FchParams->Usb.Ehci2Enable = TRUE; FchParams->Usb.Ehci2Enable = TRUE;
/* sata configuration */ /* sata configuration */
FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP
FchParams->Sata.SataDevSlpPort1 = 0; FchParams->Sata.SataDevSlpPort0 = 0;
FchParams->Sata.SataDevSlpPort1 = 0;
FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
case SataRaid: case SataRaid:
case SataAhci: case SataAhci:
case SataAhci7804: case SataAhci7804:
case SataLegacyIde: case SataLegacyIde:
FchParams->Sata.SataIdeMode = FALSE; FchParams->Sata.SataIdeMode = FALSE;
break; break;
case SataIde2Ahci: case SataIde2Ahci:
case SataIde2Ahci7804: case SataIde2Ahci7804:
default: /* SataNativeIde */ default: /* SataNativeIde */
FchParams->Sata.SataIdeMode = TRUE; FchParams->Sata.SataIdeMode = TRUE;
break; break;
}
} }
printk(BIOS_DEBUG, "Done\n"); printk(BIOS_DEBUG, "Done\n");
return AGESA_SUCCESS;
} }
static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)

1
src/mainboard/pcengines/apu2/Kconfig
View File

@ -20,7 +20,6 @@ if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \
config BOARD_SPECIFIC_OPTIONS config BOARD_SPECIFIC_OPTIONS
def_bool y def_bool y
select BINARYPI_LEGACY_WRAPPER
select CPU_AMD_PI_00730F01 select CPU_AMD_PI_00730F01
select NORTHBRIDGE_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01
select SOUTHBRIDGE_AMD_PI_AVALON select SOUTHBRIDGE_AMD_PI_AVALON

22
src/mainboard/pcengines/apu2/OemCustomize.c
View File

@ -14,7 +14,7 @@
*/ */
#include <AGESA.h> #include <AGESA.h>
#include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/agesa/state_machine.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
@ -76,25 +76,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
.DdiLinkList = NULL, .DdiLinkList = NULL,
}; };
/*---------------------------------------------------------------------------------------*/ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
)
{ {
InitEarly->GnbConfig.PcieComplexList = &PcieComplex; InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
InitEarly->PlatformConfig.CStateMode = CStateModeC6; InitEarly->PlatformConfig.CStateMode = CStateModeC6;

89
src/mainboard/pcengines/apu2/romstage.c
View File

@ -21,11 +21,8 @@
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <console/console.h> #include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/car.h> #include <cpu/amd/car.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>
#include <southbridge/amd/pi/hudson/hudson.h> #include <southbridge/amd/pi/hudson/hudson.h>
#include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/common/nuvoton.h>
@ -40,9 +37,11 @@
static void early_lpc_init(void); static void early_lpc_init(void);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void board_BeforeAgesa(struct sysinfo *cb)
{ {
u32 val; u32 val;
pci_devfn_t dev;
u32 data;
/* /*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
@ -52,85 +51,39 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
* the SoC BKDGs. Without this setting, there is no serial * the SoC BKDGs. Without this setting, there is no serial
* output. * output.
*/ */
outb(0xD2, 0xcd6); outb(0xd2, 0xcd6);
outb(0x00, 0xcd7); outb(0x00, 0xcd7);
hudson_lpc_port80(); hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30);
pci_devfn_t dev; early_lpc_init();
u32 data;
timestamp_init(timestamp_get()); hudson_clk_output_48Mhz();
timestamp_add_now(TS_START_ROMSTAGE); post_code(0x31);
post_code(0x30); dev = PCI_DEV(0, 0x14, 3);
early_lpc_init(); data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
/* enable 0x2e/0x4e IO decoding before configuring SuperIO */
pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
hudson_clk_output_48Mhz(); /* COM2 on apu5 is reserved so only COM1 should be supported */
post_code(0x31); if ((CONFIG_UART_FOR_CONSOLE == 1) &&
!CONFIG(BOARD_PCENGINES_APU5))
nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
else if (CONFIG_UART_FOR_CONSOLE == 0)
nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
dev = PCI_DEV(0, 0x14, 3);
data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
/* enable 0x2e/0x4e IO decoding before configuring SuperIO */
pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
/* COM2 on apu5 is reserved so only COM1 should be supported */
if ((CONFIG_UART_FOR_CONSOLE == 1) &&
!CONFIG(BOARD_PCENGINES_APU5))
nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
else if (CONFIG_UART_FOR_CONSOLE == 0)
nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
console_init();
}
/* Halt if there was a built in self test failure */
post_code(0x34);
report_bist_failure(bist);
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
AGESAWRAPPER(amdinitreset);
post_code(0x38);
printk(BIOS_DEBUG, "Got past avalon_early_setup\n");
post_code(0x39);
AGESAWRAPPER(amdinitearly);
/* Disable SVI2 controller to wait for command completion */ /* Disable SVI2 controller to wait for command completion */
val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C); val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C);
if (val & (1 << 30)) { if (!(val & (1 << 30))) {
printk(BIOS_DEBUG, "SVI2 Wait completion disabled\n");
} else {
printk(BIOS_DEBUG, "Disabling SVI2 Wait completion\n");
val |= (1 << 30); val |= (1 << 30);
pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val); pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val);
} }
timestamp_add_now(TS_BEFORE_INITRAM); /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
outb(0xea, 0xcd6);
post_code(0x40);
AGESAWRAPPER(amdinitpost);
/* FIXME: Detect if TSC frequency changed during raminit? */
timestamp_rescale_table(1, 4);
timestamp_add_now(TS_AFTER_INITRAM);
}
void agesa_postcar(struct sysinfo *cb)
{
//PspMboxBiosCmdDramInfo();
post_code(0x41);
AGESAWRAPPER(amdinitenv);
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7); outb(0x1, 0xcd7);
} }