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mb/intel/tglrvp: Enable Hybrid storage mode 

BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP form NVMe and Optane
Check PCIe lane configuration
Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I5fc8fa0897ad006de9ebe20115bf3033e1e1b499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
This commit is contained in:
Wonkyu Kim 2020-03-03 01:58:17 -08:00 committed by Patrick Georgi
parent ccde6be13a
commit f787e87145
2 changed files with 6 additions and 0 deletions
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3
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -37,6 +37,9 @@ chip soc/intel/tigerlake
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[10]" = "1"
# Hybrid storage mode
register "HybridStorageMode" = "1"
register "PcieClkSrcClkReq[1]" = "1"
register "PcieClkSrcClkReq[2]" = "2"
register "PcieClkSrcClkReq[3]" = "3"

3
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@ -37,6 +37,9 @@ chip soc/intel/tigerlake
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[10]" = "1"
# Hybrid storage mode
register "HybridStorageMode" = "1"
register "PcieClkSrcClkReq[1]" = "1"
register "PcieClkSrcClkReq[2]" = "2"
register "PcieClkSrcClkReq[3]" = "3"