driver/intel/fsp2_0: Add version parameter to FSP platform callback

Change-Id: Ibad1ad6bb9eedf2805981623e835db071d54c528
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/17497
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Andrey Petrov 2016-11-18 14:57:51 -08:00 committed by Aaron Durbin
parent 51c67601f1
commit f796c6e0ec
5 changed files with 5 additions and 5 deletions

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@ -41,7 +41,7 @@ void fsp_memory_init(bool s3wake);
void fsp_silicon_init(bool s3wake); void fsp_silicon_init(bool s3wake);
/* Callbacks for updating stage-specific parameters */ /* Callbacks for updating stage-specific parameters */
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd); void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version);
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd); void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd);
/* Callback after processing FSP notify */ /* Callback after processing FSP notify */

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@ -316,7 +316,7 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
die("FSPM_ARCH_UPD not found!\n"); die("FSPM_ARCH_UPD not found!\n");
/* Give SoC and mainboard a chance to update the UPD */ /* Give SoC and mainboard a chance to update the UPD */
platform_fsp_memory_init_params_cb(&fspm_upd); platform_fsp_memory_init_params_cb(&fspm_upd, hdr->fsp_revision);
/* Call FspMemoryInit */ /* Call FspMemoryInit */
fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset);

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@ -237,7 +237,7 @@ static void fill_console_params(FSPM_UPD *mupd)
} }
} }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd) void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{ {
fill_console_params(mupd); fill_console_params(mupd);
mainboard_memory_init_params(mupd); mainboard_memory_init_params(mupd);

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@ -87,7 +87,7 @@ int fill_power_state(void)
return ps->prev_sleep_state; return ps->prev_sleep_state;
} }
void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd) void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version)
{ {
FSPM_ARCH_UPD *aupd; FSPM_ARCH_UPD *aupd;
const struct device *dev; const struct device *dev;

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@ -132,7 +132,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
m_cfg->PcieRpEnableMask = mask; m_cfg->PcieRpEnableMask = mask;
} }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd) void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{ {
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;