driver/intel/fsp2_0: Add version parameter to FSP platform callback
Change-Id: Ibad1ad6bb9eedf2805981623e835db071d54c528 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17497 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -41,7 +41,7 @@ void fsp_memory_init(bool s3wake);
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void fsp_silicon_init(bool s3wake);
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void fsp_silicon_init(bool s3wake);
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/* Callbacks for updating stage-specific parameters */
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/* Callbacks for updating stage-specific parameters */
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void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd);
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void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version);
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void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd);
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void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd);
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/* Callback after processing FSP notify */
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/* Callback after processing FSP notify */
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@ -316,7 +316,7 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
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die("FSPM_ARCH_UPD not found!\n");
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die("FSPM_ARCH_UPD not found!\n");
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/* Give SoC and mainboard a chance to update the UPD */
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/* Give SoC and mainboard a chance to update the UPD */
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platform_fsp_memory_init_params_cb(&fspm_upd);
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platform_fsp_memory_init_params_cb(&fspm_upd, hdr->fsp_revision);
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/* Call FspMemoryInit */
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/* Call FspMemoryInit */
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fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset);
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fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset);
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@ -237,7 +237,7 @@ static void fill_console_params(FSPM_UPD *mupd)
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}
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}
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}
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}
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void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd)
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void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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{
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{
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fill_console_params(mupd);
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fill_console_params(mupd);
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mainboard_memory_init_params(mupd);
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mainboard_memory_init_params(mupd);
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@ -87,7 +87,7 @@ int fill_power_state(void)
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return ps->prev_sleep_state;
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return ps->prev_sleep_state;
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}
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}
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void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd)
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void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version)
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{
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{
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FSPM_ARCH_UPD *aupd;
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FSPM_ARCH_UPD *aupd;
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const struct device *dev;
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const struct device *dev;
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@ -132,7 +132,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
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m_cfg->PcieRpEnableMask = mask;
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m_cfg->PcieRpEnableMask = mask;
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}
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}
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void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd)
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void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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{
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{
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FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
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FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
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FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
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FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
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