nehalem: Restore frequency ratio registers on S3 resume
Previously registers 274/265 and 6dc/6e8 were recomputed which lead to a slightly different values. On S3 resume it needs to be a perfect match. Change-Id: I14f42c7659dde5f327979831fcb1f84ea0c78dee Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4634 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Vladimir Serbinenko
parent
f62669c966
commit
f7a42de725
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@ -102,6 +102,10 @@ struct ram_training {
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u16 timing_offset[2][2][2][9];
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u16 timing2_offset[2][2][2][9];
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u16 timing2_bounds[2][2][2][9][2];
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u8 reg274265[2][3]; /* [CHANNEL][REGISTER] */
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u8 reg2ca9_bit0;
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u32 reg_6dc;
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u32 reg_6e8;
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};
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#if !REAL
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@ -259,8 +263,6 @@ struct raminfo {
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struct ram_training training;
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u32 last_500_command[2];
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u8 reg2ca9_bit0;
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u8 reg274265[2][3]; /* [CHANNEL][REGISTER] */
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u32 delay46_ps[2];
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u32 delay54_ps[2];
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u8 revision_flag_1;
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@ -1680,6 +1682,9 @@ static void dump_timings(struct raminfo *info)
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#endif
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}
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/* Read timings and other registers that need to be restored verbatim and
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put them to CBMEM.
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*/
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static void save_timings(struct raminfo *info)
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{
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#if CONFIG_EARLY_CBMEM_INIT
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@ -1698,6 +1703,20 @@ static void save_timings(struct raminfo *info)
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train.reg_178 = read_1d0(0x178, 7);
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train.reg_10b = read_1d0(0x10b, 6);
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for (channel = 0; channel < NUM_CHANNELS; channel++) {
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u32 reg32;
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reg32 = read_mchbar32 ((channel << 10) + 0x274);
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train.reg274265[channel][0] = reg32 >> 16;
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train.reg274265[channel][1] = reg32 & 0xffff;
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train.reg274265[channel][2] = read_mchbar16 ((channel << 10) + 0x265) >> 8;
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}
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train.reg2ca9_bit0 = read_mchbar8(0x2ca9) & 1;
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train.reg_6dc = read_mchbar32 (0x6dc);
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train.reg_6e8 = read_mchbar32 (0x6e8);
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printk (BIOS_SPEW, "[6dc] = %x\n", train.reg_6dc);
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printk (BIOS_SPEW, "[6e8] = %x\n", train.reg_6e8);
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/* Save the MRC S3 restore data to cbmem */
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cbmem_recovery(0);
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mrcdata = cbmem_add
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@ -3491,6 +3510,13 @@ set_6d_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2,
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0, 1, &ratios2);
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compute_frequence_ratios(info, freq1, freq2, num_cycles_3, num_cycles_4,
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0, 1, &ratios1);
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printk (BIOS_SPEW, "[%x] <= %x\n", reg,
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ratios1.freq4_to_max_remainder | (ratios2.
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freq4_to_max_remainder
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<< 8)
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| (ratios1.divisor_f4_to_fmax << 16) | (ratios2.
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divisor_f4_to_fmax
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<< 20));
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write_mchbar32(reg,
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ratios1.freq4_to_max_remainder | (ratios2.
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freq4_to_max_remainder
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@ -3553,7 +3579,7 @@ set_2dx8_reg(struct raminfo *info, u16 reg, u8 mode, u16 freq1, u16 freq2,
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}
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}
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static void set_2dxx_series(struct raminfo *info)
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static void set_2dxx_series(struct raminfo *info, int s3resume)
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{
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set_2dx8_reg(info, 0x2d00, 0, 0x78, frequency_11(info) / 2, 1359, 1005,
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0, 1);
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@ -3581,14 +3607,24 @@ static void set_2dxx_series(struct raminfo *info)
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set_2dx8_reg(info, 0x6d8, 2, info->fsb_frequency,
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frequency_11(info) / 2, 4000, 4000, 0, 0);
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if (s3resume) {
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printk (BIOS_SPEW, "[6dc] <= %x\n", info->cached_training->reg_6dc);
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write_mchbar32(0x6dc, info->cached_training->reg_6dc);
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} else
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set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0,
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info->delay46_ps[0], 0, info->delay54_ps[0]);
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info->delay46_ps[0], 0,
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info->delay54_ps[0]);
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set_2dx8_reg(info, 0x6e0, 1, 2 * info->fsb_frequency,
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frequency_11(info), 2500, 0, 0, 0);
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set_2dx8_reg(info, 0x6e4, 1, 2 * info->fsb_frequency,
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frequency_11(info) / 2, 3500, 0, 0, 0);
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if (s3resume) {
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printk (BIOS_SPEW, "[6e8] <= %x\n", info->cached_training->reg_6e8);
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write_mchbar32(0x6e8, info->cached_training->reg_6e8);
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} else
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set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0,
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info->delay46_ps[1], 0, info->delay54_ps[1]);
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info->delay46_ps[1], 0,
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info->delay54_ps[1]);
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set_2d5x_reg(info, 0x2d58, 0x78, 0x78, 864, 1195, 762, 786, 0);
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set_2d5x_reg(info, 0x2d60, 0x195, info->fsb_frequency, 1352, 725, 455,
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470, 0);
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@ -3639,7 +3675,7 @@ static void set_274265(struct raminfo *info)
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int channel;
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delay_a_ps = 4 * halfcycle_ps(info) + 6 * fsbcycle_ps(info);
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info->reg2ca9_bit0 = 0;
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info->training.reg2ca9_bit0 = 0;
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for (channel = 0; channel < NUM_CHANNELS; channel++) {
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cycletime_ps =
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900000 / lcm(2 * info->fsb_frequency, frequency_11(info));
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@ -3690,7 +3726,7 @@ static void set_274265(struct raminfo *info)
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if (info->delay46_ps[channel] < 2500) {
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info->delay46_ps[channel] = 2500;
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info->reg2ca9_bit0 = 1;
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info->training.reg2ca9_bit0 = 1;
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}
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delay_b_ps = halfcycle_ps(info) + delay_c_ps;
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if (delay_b_ps <= delay_a_ps)
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@ -3703,25 +3739,24 @@ static void set_274265(struct raminfo *info)
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2 * halfcycle_ps(info) * delay_e_cycles;
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if (info->delay54_ps[channel] < 2500)
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info->delay54_ps[channel] = 2500;
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info->reg274265[channel][0] = delay_e_cycles;
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info->training.reg274265[channel][0] = delay_e_cycles;
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if (delay_d_ps + 7 * halfcycle_ps(info) <=
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24 * halfcycle_ps(info))
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info->reg274265[channel][1] = 0;
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info->training.reg274265[channel][1] = 0;
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else
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info->reg274265[channel][1] =
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info->training.reg274265[channel][1] =
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div_roundup(delay_d_ps + 7 * halfcycle_ps(info),
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4 * halfcycle_ps(info)) - 6;
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write_mchbar32((channel << 10) + 0x274,
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info->reg274265[channel][1] | (info->
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reg274265[channel]
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[0] << 16));
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info->reg274265[channel][2] =
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info->training.reg274265[channel][1]
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| (info->training.reg274265[channel][0] << 16));
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info->training.reg274265[channel][2] =
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div_roundup(delay_c_ps + 3 * fsbcycle_ps(info),
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4 * halfcycle_ps(info)) + 1;
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write_mchbar16((channel << 10) + 0x265,
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info->reg274265[channel][2] << 8);
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info->training.reg274265[channel][2] << 8);
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}
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if (info->reg2ca9_bit0)
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if (info->training.reg2ca9_bit0)
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write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) | 1);
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else
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write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) & ~1);
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@ -3733,12 +3768,12 @@ static void restore_274265(struct raminfo *info)
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for (channel = 0; channel < NUM_CHANNELS; channel++) {
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write_mchbar32((channel << 10) + 0x274,
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(info->reg274265[channel][0] << 16) | info->
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reg274265[channel][1]);
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(info->cached_training->reg274265[channel][0] << 16)
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| info->cached_training->reg274265[channel][1]);
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write_mchbar16((channel << 10) + 0x265,
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info->reg274265[channel][2] << 8);
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info->cached_training->reg274265[channel][2] << 8);
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}
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if (info->reg2ca9_bit0)
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if (info->cached_training->reg2ca9_bit0)
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write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) | 1);
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else
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write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) & ~1);
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@ -4145,50 +4180,29 @@ void raminit(const int s3resume)
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udelay(1000);
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info.cached_training = get_cached_training();
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if (x2ca8 == 0) {
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if (s3resume) {
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#if REAL && 0
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info.reg2ca9_bit0 = 0;
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info.reg274265[0][0] = 5;
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info.reg274265[0][1] = 5;
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info.reg274265[0][2] = 0xe;
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info.reg274265[1][0] = 5;
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info.reg274265[1][1] = 5;
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info.reg274265[1][2] = 0xe;
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info.delay46_ps[0] = 0xa86;
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info.delay46_ps[1] = 0xa86;
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info.delay54_ps[0] = 0xdc6;
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info.delay54_ps[1] = 0xdc6;
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#else
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info.reg2ca9_bit0 = 0;
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info.reg274265[0][0] = 3;
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info.reg274265[0][1] = 5;
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info.reg274265[0][2] = 0xd;
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info.reg274265[1][0] = 4;
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info.reg274265[1][1] = 5;
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info.reg274265[1][2] = 0xd;
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info.delay46_ps[0] = 0x110a;
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info.delay46_ps[1] = 0xb58;
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info.delay54_ps[0] = 0x144a;
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info.delay54_ps[1] = 0xe98;
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#endif
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restore_274265(&info);
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} else
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set_274265(&info);
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int j;
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printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", info.reg2ca9_bit0);
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if (s3resume && info.cached_training) {
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restore_274265(&info);
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printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n",
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info.cached_training->reg2ca9_bit0);
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for (i = 0; i < 2; i++)
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for (j = 0; j < 3; j++)
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printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n",
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i, j, info.reg274265[i][j]);
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i, j, info.cached_training->reg274265[i][j]);
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} else {
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set_274265(&info);
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printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n",
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info.training.reg2ca9_bit0);
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for (i = 0; i < 2; i++)
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printk(BIOS_DEBUG, "delay46_ps[%d] = %x\n", i,
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info.delay46_ps[i]);
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for (i = 0; i < 2; i++)
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printk(BIOS_DEBUG, "delay54_ps[%d] = %x\n", i,
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info.delay54_ps[i]);
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for (j = 0; j < 3; j++)
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printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n",
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i, j, info.training.reg274265[i][j]);
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}
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set_2dxx_series(&info);
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set_2dxx_series(&info, s3resume);
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if (!(deven & 8)) {
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read_mchbar32(0x2cb0);
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@ -4504,8 +4518,6 @@ void raminit(const int s3resume)
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udelay(1000);
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info.cached_training = get_cached_training();
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if (s3resume) {
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if (info.cached_training == NULL) {
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u32 reg32;
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