mainboard/intel/mohonpeak: code cleanup
Code cleanup requested in commit 90957f88
-
"mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000"
- Change com2 to COM2 in Kconfig text
- clean up includes of headers
- fix whitespace
Change-Id: I828bc4781ee7de95be5546206c5d6033b75293d9
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6607
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
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@ -94,6 +94,6 @@ config UART_FOR_CONSOLE
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int
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int
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default 1
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default 1
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help
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help
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The Mohon Peak board uses com2 (2f8) for the serial console.
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The Mohon Peak board uses COM2 (2f8) for the serial console.
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endif # BOARD_INTEL_MOHONPEAK
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endif # BOARD_INTEL_MOHONPEAK
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@ -30,15 +30,14 @@
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#include <device/pci.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ids.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/msr.h>
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#include "northbridge/intel/fsp_rangeley/northbridge.h"
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#include <southbridge/intel/fsp_rangeley/nvs.h>
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#include <northbridge/intel/fsp_rangeley/northbridge.h>
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extern const unsigned char AmlCode[];
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extern const unsigned char AmlCode[];
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#if CONFIG_HAVE_ACPI_SLIC
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#if CONFIG_HAVE_ACPI_SLIC
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unsigned long acpi_create_slic(unsigned long current);
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unsigned long acpi_create_slic(unsigned long current);
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#endif
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#endif
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#include "southbridge/intel/fsp_rangeley/nvs.h"
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static global_nvs_t *gnvs_;
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static global_nvs_t *gnvs_;
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static void acpi_create_gnvs(global_nvs_t *gnvs)
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static void acpi_create_gnvs(global_nvs_t *gnvs)
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@ -20,7 +20,7 @@
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#ifndef MOHONPEAK_GPIO_H
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#ifndef MOHONPEAK_GPIO_H
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#define MOHONPEAK_GPIO_H
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#define MOHONPEAK_GPIO_H
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#include "southbridge/intel/fsp_rangeley/gpio.h"
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#include <southbridge/intel/fsp_rangeley/gpio.h>
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/* Core GPIO */
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/* Core GPIO */
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const struct soc_gpio soc_gpio_mode = {
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const struct soc_gpio soc_gpio_mode = {
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@ -175,4 +175,4 @@ const struct soc_gpio_map gpio_map = {
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},
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},
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};
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};
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#endif
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#endif /* MOHONPEAK_GPIO_H */
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@ -18,22 +18,7 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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*/
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#include <types.h>
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#include <string.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#if CONFIG_VGA_ROM_RUN
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#include <x86emu/x86emu.h>
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#endif
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#include <pc80/mc146818rtc.h>
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <arch/interrupt.h>
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#include <boot/coreboot_tables.h>
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#include <southbridge/intel/fsp_rangeley/soc.h>
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/*
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/*
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* mainboard_enable is executed as first thing after enumerate_buses().
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* mainboard_enable is executed as first thing after enumerate_buses().
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@ -19,36 +19,27 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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*/
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#include <stdint.h>
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#include <string.h>
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#include <lib.h>
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#include <timestamp.h>
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#include <arch/io.h>
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#include <arch/io.h>
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#include <device/pci_def.h>
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#include <device/pci_def.h>
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#include <device/pnp_def.h>
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#include <device/pnp_def.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/lapic.h>
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#include <pc80/mc146818rtc.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <drivers/intel/fsp/fsp_util.h>
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#include <drivers/intel/fsp/fsp_util.h>
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#include <northbridge/intel/fsp_rangeley/northbridge.h>
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#include <southbridge/intel/fsp_rangeley/soc.h>
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#include <southbridge/intel/fsp_rangeley/soc.h>
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#include <southbridge/intel/fsp_rangeley/gpio.h>
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#include <southbridge/intel/fsp_rangeley/gpio.h>
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#include <southbridge/intel/fsp_rangeley/romstage.h>
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#include <southbridge/intel/fsp_rangeley/romstage.h>
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#include <arch/cpu.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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#include "gpio.h"
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#include "gpio.h"
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static void interrupt_routing_config(void)
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static void interrupt_routing_config(void)
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{
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{
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u32 ilb_base = pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf;
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u32 ilb_base = pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf;
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/*
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/*
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* Initialize Interrupt Routings for each device in ilb_base_address.
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* Initialize Interrupt Routings for each device in ilb_base_address.
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* IR01 map to PCIe device 0x01 ... IR31 to device 0x1F.
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* IR01 map to PCIe device 0x01 ... IR31 to device 0x1F.
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* PIRQ_A maps to IRQ 16 ... PIRQ_H maps tp IRQ 23.
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* PIRQ_A maps to IRQ 16 ... PIRQ_H maps tp IRQ 23.
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* This should match devicetree and the ACPI IRQ routing/
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* This should match devicetree and the ACPI IRQ routing/
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*/
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*/
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write32(ilb_base + ILB_ACTL, 0x0000); /* ACTL bit 2:0 SCIS IRQ9 */
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write32(ilb_base + ILB_ACTL, 0x0000); /* ACTL bit 2:0 SCIS IRQ9 */
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write16(ilb_base + ILB_IR01, 0x3210); /* IR01h IR(ABCD) - PIRQ(ABCD) */
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write16(ilb_base + ILB_IR01, 0x3210); /* IR01h IR(ABCD) - PIRQ(ABCD) */
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write16(ilb_base + ILB_IR02, 0x3210); /* IR02h IR(ABCD) - PIRQ(ABCD) */
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write16(ilb_base + ILB_IR02, 0x3210); /* IR02h IR(ABCD) - PIRQ(ABCD) */
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