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mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage 

Currently the BayHub eMMC enable pin is using the default
configuration from the baseboard, which leads to RTD3 not being able
to control the GPIO when exiting and entering suspend. To fix this,
program the GPIO in the ramstage GPIO table.

BUG=b:222436260
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
     scope enable pin while performing suspend stress and enable pin
     works as expected.
     test suspend stress 1000 cycles passed on primus.

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Casper Chang 2022-03-09 16:48:58 +08:00 committed by Tim Wawrzynczak
parent 13f49ce754
commit f7abb4fccf
2 changed files with 4 additions and 0 deletions
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2
src/mainboard/google/brya/variants/primus/gpio.c
View File

@ -49,6 +49,8 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_E3, NONE), PAD_NC(GPP_E3, NONE),
/* E7 : PROC_GP1 ==> NC */ /* E7 : PROC_GP1 ==> NC */
PAD_NC(GPP_E7, NONE), PAD_NC(GPP_E7, NONE),
/* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */
PAD_CFG_GPO(GPP_E20, 1, DEEP),
/* E21 : DDP2_CTRLDATA ==> NC */ /* E21 : DDP2_CTRLDATA ==> NC */
PAD_NC(GPP_E21, NONE), PAD_NC(GPP_E21, NONE),

2
src/mainboard/google/brya/variants/primus4es/gpio.c
View File

@ -53,6 +53,8 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_E3, NONE), PAD_NC(GPP_E3, NONE),
/* E7 : PROC_GP1 ==> NC */ /* E7 : PROC_GP1 ==> NC */
PAD_NC(GPP_E7, NONE), PAD_NC(GPP_E7, NONE),
/* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */
PAD_CFG_GPO(GPP_E20, 1, DEEP),
/* E21 : DDP2_CTRLDATA ==> NC */ /* E21 : DDP2_CTRLDATA ==> NC */
PAD_NC(GPP_E21, NONE), PAD_NC(GPP_E21, NONE),