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nb/i945/early_init.c: Add FSB800 and 1067 to Egress Port Virtual Channel 

Values based on vendor bios and suggested by Arthur Heymans for FSB1067.
FSB1067:
The ratio 1067/800 is proportional to the ratio of EPBAR32(0x2c) bits:
0x1a / 0x14 ~ 1067/800
EPVC1IST:
The ratio is also proportional to FSB ratios: 0x9c / 0xf0 ~ 533/800.

Change-Id: Ib90e8ea1b82f2fcc3b5c199cace32a7f0aff4b5c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17198
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Elyes HAOUAS 2016-10-31 18:55:04 +01:00 committed by Martin Roth
parent 1b3a6e4b14
commit f7acdf82cb
1 changed files with 18 additions and 0 deletions
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18
src/northbridge/intel/i945/early_init.c
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@ -232,8 +232,14 @@ static void i945_setup_egress_port(void)
/* Egress Port Virtual Channel 1 Configuration */ /* Egress Port Virtual Channel 1 Configuration */
reg32 = EPBAR32(0x2c); reg32 = EPBAR32(0x2c);
reg32 &= 0xffffff00; reg32 &= 0xffffff00;
if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
if ((MCHBAR32(CLKCFG) & 7) == 0)
reg32 |= 0x1a; /* 1067MHz */
}
if ((MCHBAR32(CLKCFG) & 7) == 1) if ((MCHBAR32(CLKCFG) & 7) == 1)
reg32 |= 0x0d; /* 533MHz */ reg32 |= 0x0d; /* 533MHz */
if ((MCHBAR32(CLKCFG) & 7) == 2)
reg32 |= 0x14; /* 800MHz */
if ((MCHBAR32(CLKCFG) & 7) == 3) if ((MCHBAR32(CLKCFG) & 7) == 3)
reg32 |= 0x10; /* 667MHz */ reg32 |= 0x10; /* 667MHz */
EPBAR32(0x2c) = reg32; EPBAR32(0x2c) = reg32;
@ -245,11 +251,23 @@ static void i945_setup_egress_port(void)
reg32 |= (0x0a << 16); reg32 |= (0x0a << 16);
EPBAR32(EPVC1RCAP) = reg32; EPBAR32(EPVC1RCAP) = reg32;
if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
if ((MCHBAR32(CLKCFG) & 7) == 0){ /* 1067MHz */
EPBAR32(EPVC1IST + 0) = 0x01380138;
EPBAR32(EPVC1IST + 4) = 0x01380138;
}
}
if ((MCHBAR32(CLKCFG) & 7) == 1) { /* 533MHz */ if ((MCHBAR32(CLKCFG) & 7) == 1) { /* 533MHz */
EPBAR32(EPVC1IST + 0) = 0x009c009c; EPBAR32(EPVC1IST + 0) = 0x009c009c;
EPBAR32(EPVC1IST + 4) = 0x009c009c; EPBAR32(EPVC1IST + 4) = 0x009c009c;
} }
if ((MCHBAR32(CLKCFG) & 7) == 2) { /* 800MHz */
EPBAR32(EPVC1IST + 0) = 0x00f000f0;
EPBAR32(EPVC1IST + 4) = 0x00f000f0;
}
if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */ if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */
EPBAR32(EPVC1IST + 0) = 0x00c000c0; EPBAR32(EPVC1IST + 0) = 0x00c000c0;
EPBAR32(EPVC1IST + 4) = 0x00c000c0; EPBAR32(EPVC1IST + 4) = 0x00c000c0;