intel: Remove GFXUMA and related global variables

Remove use of global variables uma_memory_base and uma_memory_size
from builds with Intel northbridges, as these variables can be kept
within the chipset or even as stack locals.

Intel platforms have no functional implemenation for option GFXUMA.
If we did implement some choice between external and integrated graphics,
it needs to be named in less obscure fashion.

Change-Id: I12f18c4ee6bc89e65a561db6c2b514956f3e2d03
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5720
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Kyösti Mälkki 2013-10-18 11:02:46 +03:00
parent 5f09807229
commit f7bfc34942
38 changed files with 12 additions and 32 deletions

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@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512
select GFXUMA
config MAINBOARD_DIR
string

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@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512
select GFXUMA
config MAINBOARD_DIR
string

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@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512
select GFXUMA
config MAINBOARD_DIR
string

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@ -38,7 +38,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_SLIC
select UDELAY_LAPIC
select BOARD_ROMSIZE_KB_1024
select GFXUMA
select CHANNEL_XOR_RANDOMIZATION
select RTL8168_ROM_DISABLE

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@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select GFXUMA
select MAINBOARD_HAS_CHROMEOS
select EARLY_CBMEM_INIT

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@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select GFXUMA
select MAINBOARD_HAS_CHROMEOS
select SERIRQ_CONTINUOUS_MODE
select MAINBOARD_HAS_NATIVE_VGA_INIT

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@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select GFXUMA
select MAINBOARD_HAS_CHROMEOS
select EARLY_CBMEM_INIT

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@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select GFXUMA
select MAINBOARD_HAS_CHROMEOS
config MAINBOARD_DIR

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@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512
select GFXUMA
config MAINBOARD_DIR
string

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@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_512
select GFXUMA
select CHANNEL_XOR_RANDOMIZATION
config MAINBOARD_DIR

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@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select MMCONF_SUPPORT
select GFXUMA
select SUPERIO_SMSC_SIO1007
select ENABLE_VMX
select EARLY_CBMEM_INIT

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@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select USE_WATCHDOG_ON_BOOT
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512
select GFXUMA
config MAINBOARD_DIR
string

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@ -33,7 +33,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_512
select GFXUMA
select CHANNEL_XOR_RANDOMIZATION
select RTL8168_ROM_DISABLE

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@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
select GFXUMA
#select MAINBOARD_HAS_CHROMEOS
select EARLY_CBMEM_INIT

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@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select UDELAY_LAPIC
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024
select GFXUMA
select BROKEN_CAR_MIGRATE
config MAINBOARD_DIR

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@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_1024
select GFXUMA
select CHANNEL_XOR_RANDOMIZATION
select OVERRIDE_CLOCK_DISABLE
select RTL8168_ROM_DISABLE

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@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select GFXUMA
select EARLY_CBMEM_INIT
select ENABLE_VMX
select HAVE_MRC

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@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select GFXUMA
select EARLY_CBMEM_INIT
# Workaround for EC/KBC IRQ1.

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@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select GFXUMA
select EARLY_CBMEM_INIT
# Workaround for EC/KBC IRQ1.

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@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select GFXUMA
select BOARD_ROMSIZE_KB_2048
select CHANNEL_XOR_RANDOMIZATION
select HAVE_ACPI_TABLES

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@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_CMOS_DEFAULT
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select GFXUMA
select BOARD_ROMSIZE_KB_8192
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME

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@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select GFXUMA
select EARLY_CBMEM_INIT
# Workaround for EC/KBC IRQ1.

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@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_CMOS_DEFAULT
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select GFXUMA
select BOARD_ROMSIZE_KB_2048
select CHANNEL_XOR_RANDOMIZATION
select HAVE_ACPI_TABLES

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@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512
select GFXUMA
config MAINBOARD_DIR
string

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@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SUPERIO_WINBOND_W83627HF
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_512
select GFXUMA
config MAINBOARD_DIR
string

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@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512
select GFXUMA
config MAINBOARD_DIR
string

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@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_IBEXPEAK
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select GFXUMA
select BOARD_ROMSIZE_KB_4096
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME

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@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_1024
select GFXUMA
config MAINBOARD_DIR
string

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@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_1024
select CHANNEL_XOR_RANDOMIZATION
select GFXUMA
select RTL8168_ROM_DISABLE
config MAINBOARD_DIR

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@ -6,7 +6,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_CHROMEOS
select CPU_INTEL_SOCKET_RPGA989
select EC_SMSC_MEC1308
select GFXUMA
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE

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@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_8192
select MAINBOARD_HAS_CHROMEOS
select CPU_INTEL_SOCKET_RPGA989
select GFXUMA
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE

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@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512
select GFXUMA
config MAINBOARD_DIR
string

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@ -41,6 +41,10 @@
static int bridge_revision_id = -1;
static u8 finished_FSP_after_pci = 0;
/* IGD UMA memory */
static uint64_t uma_memory_base = 0;
static uint64_t uma_memory_size = 0;
int bridge_silicon_revision(void)
{
if (bridge_revision_id < 0) {

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@ -73,6 +73,7 @@ static void pci_domain_set_resources(device_t dev)
{
device_t mc_dev;
int igd_memory = 0;
uint64_t uma_memory_base = 0, uma_memory_size = 0;
mc_dev = dev->link_list->children;
if (!mc_dev)

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@ -54,6 +54,7 @@ static void pci_domain_set_resources(device_t dev)
{
device_t mc_dev;
int igd_memory = 0;
uint64_t uma_memory_base = 0, uma_memory_size = 0;
mc_dev = dev->link_list->children;
if (!mc_dev)

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@ -87,6 +87,7 @@ static void pci_domain_set_resources(device_t dev)
uint8_t tolud, reg8;
uint16_t reg16;
unsigned long long tomk, tomk_stolen;
uint64_t uma_memory_base = 0, uma_memory_size = 0;
uint64_t tseg_memory_base = 0, tseg_memory_size = 0;
/* Can we find out how much memory we can use at most

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@ -39,6 +39,10 @@
static int bridge_revision_id = -1;
/* IGD UMA memory */
static uint64_t uma_memory_base = 0;
static uint64_t uma_memory_size = 0;
int bridge_silicon_revision(void)
{
if (bridge_revision_id < 0) {

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@ -99,6 +99,7 @@ static void pci_domain_set_resources(device_t dev)
u8 reg8;
u16 reg16;
unsigned long long tomk, tolud, tomk_stolen;
uint64_t uma_memory_base = 0, uma_memory_size = 0;
uint64_t tseg_memory_base = 0, tseg_memory_size = 0;
/* Can we find out how much memory we can use at most this way? */