GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/stoneyridge/early_fch: use common lpc_early_init function 

The functionality of sb_enable_lpc is implemented in the common LPC
support code as lpc_enable_controller. This gets called by the common
lpc_early_init which also calls lpc_disable_decodes and lpc_set_spibase.
The lpc_set_spibase call was already done in bootblock_fch_early_init,
so the main change in code behavior is that now lpc_disable_decodes gets
called during early FCH initialization. The lpc_enable_port80 and
sb_lpc_decode calls after the lpc_early_init code will reenable some of
the decodes.

TEST=Successfully boots on google/liara, cbmem and dmesg logs look clean

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia58a6f609fa149a6c09ed99f08bdc4f05eb56f96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66841
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2022-08-17 21:38:07 +02:00
parent e943e9fc24
commit f7d86f21e1
1 changed files with 1 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/soc/amd/stoneyridge/early_fch.c
View File

@ -9,16 +9,6 @@
#include <soc/southbridge.h>
#include <types.h>
static void sb_enable_lpc(void)
{
u8 byte;
/* Enable LPC controller */
byte = pm_io_read8(PM_LPC_GATING);
byte |= PM_LPC_ENABLE;
pm_io_write8(PM_LPC_GATING, byte);
}
static void sb_lpc_decode(void)
{
u32 tmp = 0;
@ -119,11 +109,9 @@ void bootblock_fch_early_init(void)
the GPIO registers. */
enable_acpimmio_decode_pm04();
lpc_enable_rom();
sb_enable_lpc();
lpc_early_init();
lpc_enable_port80();
sb_lpc_decode();
/* Make sure the base address is predictable */
lpc_set_spibase(SPI_BASE_ADDRESS);
fch_spi_early_init();
fch_smbus_init();
fch_enable_cf9_io();