Various cosmetics, coding style fixes, constifications (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/southbridge/via/vt8237r/chip.h

@@ -52,6 +52,7 @@ struct southbridge_via_vt8237r_config {
 
 	int ide0_enable:1;
 	int ide1_enable:1;
+
 	/* 1 = 80-pin cable */
 	int ide0_80pin_cable:1;
 	int ide1_80pin_cable:1;

src/southbridge/via/vt8237r/vt8237r.c

@@ -65,8 +65,7 @@ void dump_south(device_t dev)
 	for (i = 0; i < 256; i += 16) {
 		printk_debug("%02x: ", i);
 		for (j = 0; j < 16; j++) {
-			printk_debug("%02x ",
+			printk_debug("%02x ", pci_read_config8(dev, i + j));
-				     pci_read_config8(dev, i + j));
 		}
 		printk_debug("\n");
 	}

src/southbridge/via/vt8237r/vt8237r.h

@@ -20,7 +20,7 @@
 #ifndef SOUTHBRIDGE_VIA_VT8237R_VT8237R_H
 #define SOUTHBRIDGE_VIA_VT8237R_VT8237R_H
 
-/* Static resources for the VT8237R southbridge. */
+/* Static resources for the VT8237R southbridge */
 
 #define VT8237R_APIC_ID			0x2
 #define VT8237R_ACPI_IO_BASE		0x500
@@ -30,7 +30,7 @@
 #define VT8237R_HPET_ADDR		0xfed00000ULL
 #define VT8237R_APIC_BASE		0xfec00000ULL
 
-/* IDE specific defines */
+/* IDE */
 #define IDE_CS				0x40
 #define IDE_CONF_I			0x41
 #define IDE_CONF_II			0x42
@@ -39,7 +39,7 @@
 #define IDE_MISC_II			0x45
 #define IDE_UDMA			0x50
 
-/* SMBus specific */
+/* SMBus */
 #define VT8237R_POWER_WELL		0x94
 #define VT8237R_SMBUS_IO_BASE_REG	0xd0
 #define VT8237R_SMBUS_HOST_CONF		0xd2

src/southbridge/via/vt8237r/vt8237r_bridge.c

@@ -40,7 +40,7 @@ static void bridge_enable(struct device *dev)
 	dump_south(dev);
 }
 
-static struct device_operations bridge_ops = {
+static const struct device_operations bridge_ops = {
 	.read_resources		= pci_bus_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_bus_enable_resources,
@@ -50,7 +50,7 @@ static struct device_operations bridge_ops = {
 	.ops_pci		= 0,
 };
 
-static struct pci_driver northbridge_driver __pci_driver = {
+static const struct pci_driver northbridge_driver __pci_driver = {
 	.ops	= &bridge_ops,
 	.vendor	= PCI_VENDOR_ID_VIA,
 	.device	= PCI_DEVICE_ID_VIA_K8T890CE_BR,

src/southbridge/via/vt8237r/vt8237r_early_smbus.c

@@ -26,8 +26,8 @@
 /**
  * Print an error, should it occur. If no error, just exit.
  *
- * @param host_status The data returned on the host status register after a
+ * @param host_status The data returned on the host status register after
- * transaction is processed.
+ *		      a transaction is processed.
  * @param loops The number of times a transaction was attempted.
  */
 static void smbus_print_error(u8 host_status, int loops)
@@ -46,13 +46,13 @@ static void smbus_print_error(u8 host_status, int loops)
 	if (host_status & (1 << 2))
 		print_err("Device error\r\n");
 	if (host_status & (1 << 1))
-		print_debug("Interrupt/SMI# Completed Successfully\r\n");
+		print_debug("Interrupt/SMI# completed successfully\r\n");
 	if (host_status & (1 << 0))
 		print_err("Host busy\r\n");
 }
 
 /**
- * Wait for the smbus to become ready to process the next transaction
+ * Wait for the SMBus to become ready to process the next transaction.
  */
 static void smbus_wait_until_ready(void)
 {
@@ -64,15 +64,17 @@ static void smbus_wait_until_ready(void)
 	/* Yes, this is a mess, but it's the easiest way to do it. */
 	while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT)
 		++loops;
+
 	smbus_print_error(inb(SMBHSTSTAT), loops);
 }
 
 /**
- * Reset and take ownership of the smbus
+ * Reset and take ownership of the SMBus.
  */
 static void smbus_reset(void)
 {
 	outb(HOST_RESET, SMBHSTSTAT);
+
 	/* Datasheet says we have to read it to take ownership of SMBus. */
 	inb(SMBHSTSTAT);
 
@@ -82,10 +84,10 @@ static void smbus_reset(void)
 }
 
 /**
- * Read a byte from the smbus
+ * Read a byte from the SMBus.
  *
- * @param dimm The address location of the dimm on the smbus
+ * @param dimm The address location of the DIMM on the SMBus.
- * @param offset The offset the data is located at
+ * @param offset The offset the data is located at.
  */
 u8 smbus_read_byte(u8 dimm, u8 offset)
 {
@@ -98,6 +100,7 @@ u8 smbus_read_byte(u8 dimm, u8 offset)
 	PRINT_DEBUG("\r\n");
 
 	smbus_reset();
+
 	/* Clear host data port. */
 	outb(0x00, SMBHSTDAT0);
 	SMBUS_DELAY();
@@ -108,11 +111,10 @@ u8 smbus_read_byte(u8 dimm, u8 offset)
 	dimm |= 1;
 	outb(dimm, SMBXMITADD);
 	outb(offset, SMBHSTCMD);
+
 	/* Start transaction, byte data read. */
 	outb(0x48, SMBHSTCTL);
-
 	SMBUS_DELAY();
-
 	smbus_wait_until_ready();
 
 	val = inb(SMBHSTDAT0);
@@ -138,18 +140,18 @@ void enable_smbus(void)
 				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
 
 	if (dev == PCI_DEV_INVALID)
-		die("Power Management Controller not found\r\n");
+		die("Power management controller not found\r\n");
 
 	/* 7 = SMBus Clock from RTC 32.768KHz
 	 * 5 = Internal PLL reset from susp
 	 */
 	pci_write_config8(dev, VT8237R_POWER_WELL, 0xa0);
 
-	/* Enable SMBus */
+	/* Enable SMBus. */
 	pci_write_config16(dev, VT8237R_SMBUS_IO_BASE_REG,
 			   VT8237R_SMBUS_IO_BASE | 0x1);
 
-	/* SMBus Host Configuration, enable */
+	/* SMBus Host Configuration, enable. */
 	pci_write_config8(dev, VT8237R_SMBUS_HOST_CONF, 0x01);
 
 	/* Make it work for I/O. */
@@ -162,17 +164,17 @@ void enable_smbus(void)
 }
 
 /**
- * A fixup for some systems that need time for the smbus to "warm up". This is 
+ * A fixup for some systems that need time for the SMBus to "warm up". This is 
- * needed on some vt823x based systems, where the smbus spurts out bad data for 
+ * needed on some VT823x based systems, where the SMBus spurts out bad data for 
- * a short time after power on. This has been seen on the Via Epia-series and 
+ * a short time after power on. This has been seen on the VIA Epia series and 
  * Jetway J7F2-series. It reads the ID byte from SMBus, looking for 
  * known-good data from a slot/address. Exits on either good data or a timeout.
  *
- * This should probably go into some global file, but one would need to be 
+ * TODO: This should probably go into some global file, but one would need to
- * created just for it. If some other chip needs/wants it, we can worry about it
+ *       be created just for it. If some other chip needs/wants it, we can
- * then.
+ *       worry about it then.
  *
- * @param ctrl The memory controller and smbus addresses
+ * @param ctrl The memory controller and SMBus addresses.
  */
 void smbus_fixup(const struct mem_controller *ctrl)
 {
@@ -181,24 +183,31 @@ void smbus_fixup(const struct mem_controller *ctrl)
 
 	ram_slots = ARRAY_SIZE(ctrl->channel0);
 	if (!ram_slots) {
-		print_err("smbus_fixup thinks there are no ram slots!\r\n");
+		print_err("smbus_fixup() thinks there are no RAM slots!\r\n");
 		return;
 	}
 
-	PRINT_DEBUG("Waiting for smbus to warm up");
+	PRINT_DEBUG("Waiting for SMBus to warm up");
 
-	/* Bad SPD data should be either 0 or 0xff, but YMMV. So we look for the
+	/*
-	 * ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between).
+	 * Bad SPD data should be either 0 or 0xff, but YMMV. So we look for
-	 * vt8237r has only been seen on DDR and DDR2 based systems, so far */
+	 * the ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between).
+	 * VT8237R has only been seen on DDR and DDR2 based systems, so far.
+	 */
 	for (i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) ||
-			(result > SPD_MEMORY_TYPE_SDRAM_DDR3))); i++)
+				(result > SPD_MEMORY_TYPE_SDRAM_DDR3))); i++) {
-	{
+
-		if (current_slot > ram_slots) current_slot = 0;
+		if (current_slot > ram_slots)
+			current_slot = 0;
+
 		result = smbus_read_byte(ctrl->channel0[current_slot],
 					 SPD_MEMORY_TYPE);
 		current_slot++;
 		PRINT_DEBUG(".");
 	}
-	if (i >= SMBUS_TIMEOUT)	print_err("SMBus timed out while warming up\r\n");
+
-	else PRINT_DEBUG("Done\r\n");	
+	if (i >= SMBUS_TIMEOUT)
+		print_err("SMBus timed out while warming up\r\n");
+	else
+		PRINT_DEBUG("Done\r\n");
 }

src/southbridge/via/vt8237r/vt8237r_ide.c

@@ -92,7 +92,7 @@ static void ide_init(struct device *dev)
 	pci_write_config32(dev, IDE_UDMA, cablesel);
 }
 
-static struct device_operations ide_ops = {
+static const struct device_operations ide_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
@@ -101,7 +101,7 @@ static struct device_operations ide_ops = {
 	.ops_pci		= 0,
 };
 
-static struct pci_driver northbridge_driver __pci_driver = {
+static const struct pci_driver northbridge_driver __pci_driver = {
 	.ops	= &ide_ops,
 	.vendor	= PCI_VENDOR_ID_VIA,
 	.device	= PCI_DEVICE_ID_VIA_82C586_1,

src/southbridge/via/vt8237r/vt8237r_lpc.c

@@ -335,7 +335,7 @@ static void southbridge_init(struct device *dev)
 	init_keyboard(dev);
 }
 
-static struct device_operations vt8237r_lpc_ops = {
+static const struct device_operations vt8237r_lpc_ops = {
 	.read_resources		= vt8237r_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= vt8237r_enable_resources,
@@ -343,7 +343,7 @@ static struct device_operations vt8237r_lpc_ops = {
 	.scan_bus		= scan_static_bus,
 };
 
-static struct pci_driver lpc_driver __pci_driver = {
+static const struct pci_driver lpc_driver __pci_driver = {
 	.ops	= &vt8237r_lpc_ops,
 	.vendor	= PCI_VENDOR_ID_VIA,
 	.device	= PCI_DEVICE_ID_VIA_VT8237R_LPC,

src/southbridge/via/vt8237r/vt8237r_sata.c

@@ -42,7 +42,7 @@ static void sata_init(struct device *dev)
 	pci_write_config8(dev, SATA_MISC_CTRL, reg);
 }
 
-static struct device_operations sata_ops = {
+static const struct device_operations sata_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
@@ -51,7 +51,7 @@ static struct device_operations sata_ops = {
 	.ops_pci		= 0,
 };
 
-static struct pci_driver northbridge_driver __pci_driver = {
+static const struct pci_driver northbridge_driver __pci_driver = {
 	.ops	= &sata_ops,
 	.vendor	= PCI_VENDOR_ID_VIA,
 	.device	= PCI_DEVICE_ID_VIA_VT6420_SATA,