Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . Factor out the decision whether to update northbridge frequency and voltage because there was the same code in 3 places and so we can later modify it in one place. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -280,6 +280,7 @@ static void config_acpi_pwr_state_ctrl_regs(device_t dev) {
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pci_write_config32(dev, 0x84, dword);
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dword = 0xE600A681;
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pci_write_config32(dev, 0x80, dword);
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}
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static void prep_fid_change(void)
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@ -503,25 +504,12 @@ static void transitionVid(u32 targetVid, u8 dev, u8 isNb)
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}
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}
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static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid)
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static u32 needs_NB_COF_VID_update(void)
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{
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device_t dev;
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u32 vid_max;
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u32 fid_max;
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u8 nb_cof_vid_update;
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u8 pvimode;
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u32 reg1fc;
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u32 send;
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u8 nodes;
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u8 i;
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printk(BIOS_DEBUG, "FIDVID on AP: %02x\n", apicid);
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/* Steps 1-6 of BIOS NB COF and VID Configuration
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* for SVI and Single-Plane PVI Systems.
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*/
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/* If any node has nb_cof_vid_update set all nodes need an update. */
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nodes = get_nodes();
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nb_cof_vid_update = 0;
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@ -531,6 +519,26 @@ static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid)
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break;
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}
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}
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return nb_cof_vid_update;
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}
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static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid)
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{
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device_t dev;
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u32 vid_max;
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u32 fid_max;
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u8 nb_cof_vid_update = needs_NB_COF_VID_update();
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u8 pvimode;
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u32 reg1fc;
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u32 send;
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printk(BIOS_DEBUG, "FIDVID on AP: %02x\n", apicid);
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/* Steps 1-6 of BIOS NB COF and VID Configuration
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* for SVI and Single-Plane PVI Systems.
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*/
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dev = NODE_PCI(nodeid, 3);
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pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1;
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@ -710,23 +718,13 @@ static void init_fidvid_stage2(u32 apicid, u32 nodeid)
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u32 reg1fc;
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u32 dtemp;
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u32 nbvid;
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u8 nb_cof_vid_update;
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u8 nodes;
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u8 nb_cof_vid_update = needs_NB_COF_VID_update();
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u8 NbVidUpdateAll;
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u8 i;
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u8 pvimode;
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/* After warm reset finish the fid/vid setup for all cores. */
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/* If any node has nb_cof_vid_update set all nodes need an update. */
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nodes = get_nodes();
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nb_cof_vid_update = 0;
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for (i = 0; i < nodes; i++) {
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if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) {
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nb_cof_vid_update = 1;
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break;
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}
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}
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dev = NODE_PCI(nodeid, 3);
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pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1;
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@ -788,7 +786,7 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
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device_t dev;
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u32 vid_max;
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u32 fid_max=0;
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u8 nb_cof_vid_update;
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u8 nb_cof_vid_update = needs_NB_COF_VID_update();
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u32 reg1fc;
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u8 pvimode;
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@ -801,15 +799,6 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
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* for SVI and Single-Plane PVI Systems.
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*/
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/* If any node has nb_cof_vid_update set all nodes need an update. */
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nb_cof_vid_update = 0;
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for (i = 0; i < nodes; i++) {
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if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) {
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nb_cof_vid_update = 1;
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break;
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}
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}
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dev = NODE_PCI(0, 3);
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pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1;
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reg1fc = pci_read_config32(dev, 0x1FC);
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