Various small fixes to make the Tyan S1846 match the format of
the other supported 440BX boards. Fix up totally b0rked static device tree in Config.lb. Drop useless and duplicated failover.c, use global one. Make CPU init actually work (result: massive speed-up). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
9fab090e97
commit
f7f6046f0a
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@ -1,173 +1,131 @@
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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## This file is part of the LinuxBIOS project.
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##
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## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
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else
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
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default ROM_SECTION_OFFSET = 0
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end
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##
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up linuxBIOS,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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default XIP_ROM_SIZE=65536
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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##
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## Set all of the defaults for an x86 architecture
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##
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
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+ ROM_SECTION_OFFSET + 1)
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default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
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default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
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default XIP_ROM_SIZE = 64 * 1024
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default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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#if HAVE_PIRQ_TABLE object irq_tables.o end
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#object reset.o
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##
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## Romcc output
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##
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if HAVE_PIRQ_TABLE
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object irq_tables.o
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end
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c ./romcc"
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action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
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action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(MAINBOARD)/failover.c ./romcc"
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action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
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action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c ./romcc"
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action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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makerule ./auto.E
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# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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depends "$(MAINBOARD)/auto.c ./romcc"
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action "./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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makerule ./auto.inc
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# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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depends "$(MAINBOARD)/auto.c ./romcc"
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action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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action "./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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###
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit cpu/x86/mmx/enable_mmx.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/x86/mmx/disable_mmx.inc
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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chip northbridge/intel/i440bx # Northbridge
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device pci_domain 0 on
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device apic_cluster 0 on # APIC cluster
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chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
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device apic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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device pci 0.0 on end # Host bridge
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device pci 1.0 on end # AGP bridge
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device pci 1.0 on end # PCI/AGP bridge
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chip southbridge/intel/i82371eb # Southbridge
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device pci 7.0 on # ISA bridge
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chip superio/nsc/pc87309 # Super I/O
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device pnp 2e.5 on # PS/2 keyboard (+ mouse?)
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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# irq 0x72 = 12
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end
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device pnp 2e.b on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.c on # Com2 / IR
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.d on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.e on # Floppy
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.f on # PS/2 mouse
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device pnp 2e.1 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 on # COM2 / IR
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.3 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.4 on # Power management
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end
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device pnp 2e.5 on # PS/2 mouse
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irq 0x70 = 12
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end
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device pnp 2e.6 on # PS/2 keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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end
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end
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device pci 7.1 on end # IDE
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device pci 7.2 on end # USB
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device pci 7.1 on end # IDE
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device pci 7.2 on end # USB
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device pci 7.3 on end # ACPI
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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end
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end
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chip cpu/intel/slot_2 # CPU
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end
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end
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@ -1,3 +1,24 @@
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##
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## This file is part of the LinuxBIOS project.
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##
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## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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||||
## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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||||
## This program is distributed in the hope that it will be useful,
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||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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@ -26,6 +47,7 @@ uses _ROMBASE
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uses _RAMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses HAVE_MP_TABLE
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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@ -37,113 +59,41 @@ uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses CONFIG_UDELAY_TSC
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uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PART_NUMBER
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_PCI_ROM_RUN
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE = 256*1024
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###
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### Build options
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###
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|
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##
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## Build code for the fallback boot
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##
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default HAVE_FALLBACK_BOOT=1
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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default HAVE_HARD_RESET=0
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=0
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default IRQ_SLOT_COUNT=4
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##
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## Build code to export a CMOS option table
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##
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default HAVE_OPTION_TABLE=0
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###
|
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### LinuxBIOS layout values
|
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###
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|
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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default ROM_SIZE = 256 * 1024
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default HAVE_FALLBACK_BOOT = 1
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default HAVE_MP_TABLE = 0
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default HAVE_HARD_RESET = 0
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default CONFIG_UDELAY_TSC = 1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
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default HAVE_PIRQ_TABLE = 1
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default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
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default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
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default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
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default ROM_IMAGE_SIZE = 64 * 1024
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default FALLBACK_SIZE = 128 * 1024
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##
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## Use a small 8K stack
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##
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default STACK_SIZE=0x2000
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##
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## Use a small 16K heap
|
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##
|
||||
default HEAP_SIZE=0x4000
|
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##
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## Only use the option table in a normal image
|
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##
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default STACK_SIZE = 8 * 1024
|
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default HEAP_SIZE = 16 * 1024
|
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default HAVE_OPTION_TABLE = 0
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#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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default USE_OPTION_TABLE = 0
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default _RAMBASE = 0x00004000
|
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default CONFIG_ROM_PAYLOAD = 1
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##
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## The default compiler
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##
|
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default CROSS_COMPILE=""
|
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default CC="$(CROSS_COMPILE)gcc -m32"
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default HOSTCC="gcc"
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##
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## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
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## Select the serial console baud rate
|
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default TTYS0_BAUD=115200
|
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#default TTYS0_BAUD=57600
|
||||
#default TTYS0_BAUD=38400
|
||||
#default TTYS0_BAUD=19200
|
||||
#default TTYS0_BAUD=9600
|
||||
#default TTYS0_BAUD=4800
|
||||
#default TTYS0_BAUD=2400
|
||||
#default TTYS0_BAUD=1200
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||||
|
||||
# Select the serial console base port
|
||||
default TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
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default TTYS0_LCS=0x3
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||||
|
||||
##
|
||||
### Select the linuxBIOS loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default DEFAULT_CONSOLE_LOGLEVEL=9
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||||
## At a maximum only compile in this level of debugging
|
||||
default MAXIMUM_CONSOLE_LOGLEVEL=9
|
||||
|
||||
default CONFIG_UDELAY_TSC=1
|
||||
default CROSS_COMPILE = ""
|
||||
default CC = "$(CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default TTYS0_BAUD = 115200
|
||||
default TTYS0_BASE = 0x3f8
|
||||
default TTYS0_LCS = 0x3 # 8n1
|
||||
default DEFAULT_CONSOLE_LOGLEVEL = 9
|
||||
default MAXIMUM_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_CONSOLE_VGA = 1
|
||||
default CONFIG_PCI_ROM_RUN = 1
|
||||
|
||||
end
|
||||
|
||||
|
|
|
|||
|
|
@ -31,12 +31,12 @@
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|||
#include "ram/ramtest.c"
|
||||
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
|
||||
#include "northbridge/intel/i440bx/raminit.h"
|
||||
#include "mainboard/bitworks/ims/debug.c" // FIXME
|
||||
#include "mainboard/asus/mew-vm/debug.c" /* FIXME */
|
||||
#include "pc80/udelay_io.c"
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||||
#include "lib/delay.c"
|
||||
#include "superio/nsc/pc87309/pc87309_early_serial.c"
|
||||
#include "cpu/x86/mtrr/earlymtrr.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include "superio/nsc/pc87309/pc87309_early_serial.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, PC87309_SP1)
|
||||
|
||||
|
|
@ -49,64 +49,24 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
|
|||
#include "northbridge/intel/i440bx/debug.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
||||
static void enable_mainboard_devices(void)
|
||||
{
|
||||
device_t dev = pci_locate_device(PCI_ID(0x8086, 0x7110), 0);
|
||||
|
||||
if (dev == PCI_DEV_INVALID) {
|
||||
die("Southbridge not found!\n");
|
||||
} else {
|
||||
print_debug("Southbridge found!\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller memctrl[] = {
|
||||
{
|
||||
.d0 = PCI_DEV(0, 0, 0),
|
||||
.channel0 = {0x50, 0x51, 0x52, 0x53},
|
||||
},
|
||||
}
|
||||
};
|
||||
|
||||
/* Skip this if there was a built in self test failure. */
|
||||
if (bist == 0) {
|
||||
if (bist == 0)
|
||||
early_mtrr_init();
|
||||
}
|
||||
|
||||
pc87309_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure. */
|
||||
report_bist_failure(bist);
|
||||
|
||||
enable_mainboard_devices();
|
||||
|
||||
enable_smbus();
|
||||
|
||||
dump_spd_registers(&memctrl[0]);
|
||||
|
||||
/* dump_spd_registers(&memctrl[0]); */
|
||||
sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
|
||||
|
||||
/* Check whether RAM is working.
|
||||
*
|
||||
* Do _not_ check the area from 640 KB - 768 KB, as that's not really
|
||||
* RAM, but rather reserved for the 'Video Buffer Area'.
|
||||
*
|
||||
* Other stuff in the range from 640 KB - 1 MB:
|
||||
*
|
||||
* - 640 KB - 768 KB: Video Buffer Area
|
||||
* - 768 KB - 896 KB: Expansion Area
|
||||
* - 896 KB - 960 KB: Extended System BIOS Area
|
||||
* - 960 KB - 1 MB: Memory (BIOS Area) - System BIOS Area
|
||||
*
|
||||
* Trying to check these areas will usually fail, too. However, you
|
||||
* probably can set the PAM registers of the northbridge to map
|
||||
* those areas to RAM (read/write). In that case you can use the
|
||||
* range from 768 KB - 1 MB as normal RAM, and thus check it here.
|
||||
*/
|
||||
ram_check(0x00000000, 0x0009ffff); /* 0 - 640 KB */
|
||||
ram_check(0x000c0000, 0x00100000); /* 768 KB - 1 MB */
|
||||
// ram_check(0x00100000, 0x007c0000); /* 1 MB - 64 MB */
|
||||
/* ram_check(0, 640 * 1024); */
|
||||
}
|
||||
|
|
|
|||
|
|
@ -19,6 +19,4 @@
|
|||
*/
|
||||
|
||||
extern struct chip_operations mainboard_tyan_s1846_ops;
|
||||
|
||||
struct mainboard_tyan_s1846_config {
|
||||
};
|
||||
struct mainboard_tyan_s1846_config {};
|
||||
|
|
|
|||
|
|
@ -1,32 +0,0 @@
|
|||
#define ASSEMBLY 1
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include "arch/romcc_io.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
|
||||
static unsigned long main(unsigned long bist)
|
||||
{
|
||||
/* This is the primary cpu how should I boot? */
|
||||
if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
normal_image:
|
||||
asm volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
cpu_reset:
|
||||
asm volatile ("jmp __cpu_reset"
|
||||
: /* outputs */
|
||||
: "a"(bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
fallback_image:
|
||||
return bist;
|
||||
}
|
||||
|
|
@ -22,23 +22,30 @@ target s1846
|
|||
mainboard tyan/s1846
|
||||
|
||||
option ROM_SIZE = 256 * 1024
|
||||
option FALLBACK_SIZE = ROM_SIZE
|
||||
|
||||
# romimage "normal"
|
||||
# option USE_FALLBACK_IMAGE = 0
|
||||
# option ROM_IMAGE_SIZE = 56 * 1024
|
||||
# option LINUXBIOS_EXTRA_VERSION = ".0Normal"
|
||||
# payload /tmp/filo.elf
|
||||
# # payload /tmp/memtest
|
||||
# end
|
||||
option MAINBOARD_VENDOR = "Tyan"
|
||||
option MAINBOARD_PART_NUMBER = "S1846"
|
||||
|
||||
# TODO: Add/fix PIRQ table.
|
||||
option HAVE_PIRQ_TABLE = 0
|
||||
option IRQ_SLOT_COUNT = 0 # FIXME
|
||||
|
||||
option DEFAULT_CONSOLE_LOGLEVEL = 9
|
||||
option MAXIMUM_CONSOLE_LOGLEVEL = 9
|
||||
|
||||
option CONFIG_CONSOLE_VGA = 1
|
||||
option CONFIG_PCI_ROM_RUN = 1
|
||||
|
||||
romimage "normal"
|
||||
option USE_FALLBACK_IMAGE = 0
|
||||
option LINUXBIOS_EXTRA_VERSION = ".0Normal"
|
||||
payload /tmp/filo.elf
|
||||
end
|
||||
|
||||
romimage "fallback"
|
||||
option USE_FALLBACK_IMAGE = 1
|
||||
option ROM_IMAGE_SIZE = 56 * 1024
|
||||
option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
|
||||
payload /tmp/filo.elf
|
||||
# payload /tmp/memtest
|
||||
end
|
||||
|
||||
# buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
|
||||
buildrom ./linuxbios.rom ROM_SIZE "fallback"
|
||||
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
|
||||
|
|
|
|||
Loading…
Reference in New Issue