soc/intel/alderlake: Add ADL-P 4+4 with 28W TDP

Add the 28W TDP version of the ADL-P with MCHID 0x4629.

Verified that all 28W SoCs have the same PL1/PL2 defined
in Intel document #655258 "12th Generation Intel Core
Processors Datasheet, Volume 1 of 2".

Fixes the error seen in coreboot log:
[ERROR] unknown SA ID: 0x4629, skipped power Limit Configuration

Change-Id: Iad676f083dfd1cceb4df9435d467dc0f31a63f80
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>

src/mainboard/google/brya/variants/aurash/overridetree.cb

@@ -50,7 +50,7 @@ chip soc/intel/alderlake
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 25,
 	}"
-	register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
+	register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
 		.tdp_pl1_override = 64,
 	}"
 	device domain 0 on

src/mainboard/google/brya/variants/banshee/overridetree.cb

@@ -87,7 +87,7 @@ chip soc/intel/alderlake
 
 	register "tcc_offset" = "10"     # TCC of 90
 
-	register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
+	register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
 		.tdp_pl1_override = 30,
 		.tdp_pl2_override = 60,
 		.tdp_pl4 = 90,

src/mainboard/google/brya/variants/kano/overridetree.cb

@@ -83,7 +83,7 @@ chip soc/intel/alderlake
 		},
 	}"
 
-	register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
+	register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
 		.tdp_pl1_override = 20,
 		.tdp_pl2_override = 43,
 		.tdp_pl4 = 105,

src/mainboard/google/brya/variants/moli/overridetree.cb

@@ -51,7 +51,7 @@ chip soc/intel/alderlake
 	register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{
 		.tdp_pl1_override = 55,
 	}"
-	register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
+	register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
 		.tdp_pl1_override = 64,
 	}"
 	device domain 0 on

src/mainboard/google/brya/variants/zydron/overridetree.cb

@@ -83,7 +83,7 @@ chip soc/intel/alderlake
 		},
 	}"
 
-	register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
+	register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
 		.tdp_pl1_override = 20,
 		.tdp_pl2_override = 43,
 		.tdp_pl4 = 105,

src/mainboard/starlabs/starbook/variants/adl/devtree.c

@@ -16,7 +16,7 @@ void devtree_update(void)
 	common_config = chip_get_common_soc_structure();
 
 	struct soc_power_limits_config *soc_conf_10core =
-		&cfg->power_limits_config[ADL_P_282_482_28W_CORE];
+		&cfg->power_limits_config[ADL_P_282_442_482_28W_CORE];
 
 	struct soc_power_limits_config *soc_conf_12core =
 		&cfg->power_limits_config[ADL_P_682_28W_CORE];

src/mainboard/system76/adl/variants/darp8/overridetree.cb

@@ -1,7 +1,7 @@
 chip soc/intel/alderlake
 	# HACK: Limit PL4 to PL2 to prevent power-off when system is booted on
 	# battery power. This seems to only happen with the i7 units.
-	register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
+	register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
 		.tdp_pl1_override = 20,
 		.tdp_pl2_override = 56,
 		.tdp_pl4 = 56, // FIXME: Set to 65

src/mainboard/system76/adl/variants/galp6/overridetree.cb

@@ -1,5 +1,5 @@
 chip soc/intel/alderlake
-	register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
+	register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
 		.tdp_pl1_override = 28,
 		.tdp_pl2_override = 60,
 		.tdp_pl4 = 90,

src/soc/intel/alderlake/chip.h

@@ -42,7 +42,7 @@ struct ibecc_config {
 /* Types of different SKUs */
 enum soc_intel_alderlake_power_limits {
 	ADL_P_142_242_282_15W_CORE,
-	ADL_P_282_482_28W_CORE,
+	ADL_P_282_442_482_28W_CORE,
 	ADL_P_682_28W_CORE,
 	ADL_P_442_482_45W_CORE,
 	ADL_P_642_682_45W_CORE,
@@ -102,13 +102,14 @@ static const struct {
 	{ PCI_DID_INTEL_ADL_P_ID_10, ADL_P_142_242_282_15W_CORE, TDP_15W },
 	{ PCI_DID_INTEL_ADL_P_ID_7, ADL_P_142_242_282_15W_CORE, TDP_15W },
 	{ PCI_DID_INTEL_ADL_P_ID_6, ADL_P_142_242_282_15W_CORE, TDP_15W },
-	{ PCI_DID_INTEL_ADL_P_ID_7, ADL_P_282_482_28W_CORE, TDP_28W },
-	{ PCI_DID_INTEL_ADL_P_ID_5, ADL_P_282_482_28W_CORE, TDP_28W },
+	{ PCI_DID_INTEL_ADL_P_ID_7, ADL_P_282_442_482_28W_CORE, TDP_28W },
+	{ PCI_DID_INTEL_ADL_P_ID_5, ADL_P_282_442_482_28W_CORE, TDP_28W },
 	{ PCI_DID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W },
 	{ PCI_DID_INTEL_ADL_P_ID_5, ADL_P_442_482_45W_CORE, TDP_45W },
 	{ PCI_DID_INTEL_ADL_P_ID_4, ADL_P_642_682_45W_CORE, TDP_45W },
 	{ PCI_DID_INTEL_ADL_P_ID_3, ADL_P_642_682_45W_CORE, TDP_45W },
 	{ PCI_DID_INTEL_ADL_P_ID_1, ADL_P_442_482_45W_CORE, TDP_45W },
+	{ PCI_DID_INTEL_ADL_P_ID_1, ADL_P_282_442_482_28W_CORE, TDP_28W },
 	{ PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W },
 	{ PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W },
 	{ PCI_DID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W },

src/soc/intel/alderlake/chipset.cb

@@ -8,7 +8,7 @@ chip soc/intel/alderlake
 		.tdp_pl4 = 123,
 	}"
 
-	register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
+	register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
 		.tdp_pl1_override = 28,
 		.tdp_pl2_override = 64,
 		.tdp_pl4 = 90,