soc/amd/stoneyridge/acpi/sb_fch: use existing base address defines

TEST=Identical timeless build for amd/gardenia.

Change-Id: I04952cdbbe7893f35a674a156a9bc22202fbdc2f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48311
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2020-12-04 22:57:44 +01:00
parent f914dcf3dd
commit f824a9be0b
1 changed files with 3 additions and 3 deletions

View File

@ -30,7 +30,7 @@ Device (GPIO)
{ {
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
{ 7 } { 7 }
Memory32Fixed (ReadWrite, 0xFED81500, 0x300) Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x300)
}) })
Method (_STA, 0x0, NotSerialized) Method (_STA, 0x0, NotSerialized)
@ -46,7 +46,7 @@ Device (FUR0)
Name (_CRS, ResourceTemplate() Name (_CRS, ResourceTemplate()
{ {
IRQ (Edge, ActiveHigh, Exclusive) { 10 } IRQ (Edge, ActiveHigh, Exclusive) { 10 }
Memory32Fixed (ReadWrite, 0xFEDC6000, 0x2000) Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x2000)
}) })
Method (_STA, 0x0, NotSerialized) Method (_STA, 0x0, NotSerialized)
{ {
@ -60,7 +60,7 @@ Device (FUR1) {
Name (_CRS, ResourceTemplate() Name (_CRS, ResourceTemplate()
{ {
IRQ (Edge, ActiveHigh, Exclusive) { 11 } IRQ (Edge, ActiveHigh, Exclusive) { 11 }
Memory32Fixed (ReadWrite, 0xFEDC8000, 0x2000) Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x2000)
}) })
Method (_STA, 0x0, NotSerialized) Method (_STA, 0x0, NotSerialized)
{ {