soc/amd/stoneyridge/acpi/sb_fch: use existing base address defines
TEST=Identical timeless build for amd/gardenia. Change-Id: I04952cdbbe7893f35a674a156a9bc22202fbdc2f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48311 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -30,7 +30,7 @@ Device (GPIO)
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{
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{
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
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{ 7 }
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{ 7 }
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Memory32Fixed (ReadWrite, 0xFED81500, 0x300)
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Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x300)
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})
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})
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Method (_STA, 0x0, NotSerialized)
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Method (_STA, 0x0, NotSerialized)
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@ -46,7 +46,7 @@ Device (FUR0)
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Name (_CRS, ResourceTemplate()
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Name (_CRS, ResourceTemplate()
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{
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{
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IRQ (Edge, ActiveHigh, Exclusive) { 10 }
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IRQ (Edge, ActiveHigh, Exclusive) { 10 }
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Memory32Fixed (ReadWrite, 0xFEDC6000, 0x2000)
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Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x2000)
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})
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})
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Method (_STA, 0x0, NotSerialized)
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Method (_STA, 0x0, NotSerialized)
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{
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{
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@ -60,7 +60,7 @@ Device (FUR1) {
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Name (_CRS, ResourceTemplate()
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Name (_CRS, ResourceTemplate()
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{
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{
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IRQ (Edge, ActiveHigh, Exclusive) { 11 }
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IRQ (Edge, ActiveHigh, Exclusive) { 11 }
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Memory32Fixed (ReadWrite, 0xFEDC8000, 0x2000)
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Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x2000)
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})
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})
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Method (_STA, 0x0, NotSerialized)
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Method (_STA, 0x0, NotSerialized)
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{
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{
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