Glados: Update Serial IO modes in devicetree
This patch updates the Serial IO modes for UART2 to PCI mode in devicetree for glados board. Also we switch over to CONSOLE_SERIAL8250MEM_32 here. 8-bit legacy UART will stop working after devicetree change. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for glados and tested LPSS logs on glados. CQ-DEPEND=CL:284881 CL:284882 CL:284883 Change-Id: I433979c852c80848c006ef089b43d75a17e761c5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c37519e0762801cbb9b547b538b385c84299189 Original-Change-Id: I2faec08d089e407c5ab9838bea980553f49821c4 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284826 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/11002 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -16,7 +16,7 @@ chip soc/intel/skylake
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[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
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[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
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[PchSerialIoIndexUart0] = PchSerialIoPci, \
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[PchSerialIoIndexUart0] = PchSerialIoPci, \
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[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
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[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
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[PchSerialIoIndexUart2] = PchSerialIoLegacyUart, \
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[PchSerialIoIndexUart2] = PchSerialIoPci, \
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}"
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}"
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# Enable Root port 1 and 5.
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# Enable Root port 1 and 5.
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@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS
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select CACHE_ROM
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select CACHE_ROM
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select CAR_MIGRATION
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select CAR_MIGRATION
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select CONSOLE_SERIAL8250MEM
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select CONSOLE_SERIAL8250MEM
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select CONSOLE_SERIAL8250MEM_32
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select COLLECT_TIMESTAMPS
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select COLLECT_TIMESTAMPS
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select CPU_MICROCODE_IN_CBFS
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select CPU_MICROCODE_IN_CBFS
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