spd.h: Move enum ddr3_module_type to ddr3.h
Move specific enum ddr3_module_type to <device/dram/ddr3.h>. Change-Id: I8fd7892dda26158a5bdd6cd4972c7859a252153e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71547 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -533,29 +533,7 @@ enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, const u16 selected
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dimm->dimm_num = slot;
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dimm->dimm_num = slot;
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memcpy(dimm->module_part_number, info->part_number, 16);
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memcpy(dimm->module_part_number, info->part_number, 16);
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dimm->mod_id = info->manufacturer_id;
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dimm->mod_id = info->manufacturer_id;
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dimm->mod_type = info->dimm_type;
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switch (info->dimm_type) {
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case SPD_DDR3_DIMM_TYPE_SO_DIMM:
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dimm->mod_type = DDR3_SPD_SODIMM;
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break;
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case SPD_DDR3_DIMM_TYPE_72B_SO_CDIMM:
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dimm->mod_type = DDR3_SPD_72B_SO_CDIMM;
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break;
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case SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM:
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dimm->mod_type = DDR3_SPD_72B_SO_RDIMM;
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break;
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case SPD_DDR3_DIMM_TYPE_UDIMM:
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dimm->mod_type = DDR3_SPD_UDIMM;
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break;
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case SPD_DDR3_DIMM_TYPE_RDIMM:
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dimm->mod_type = DDR3_SPD_RDIMM;
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break;
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case SPD_DDR3_DIMM_TYPE_UNDEFINED:
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default:
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dimm->mod_type = SPD_UNDEFINED;
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break;
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}
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dimm->bus_width = MEMORY_BUS_WIDTH_64; // non-ECC only
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dimm->bus_width = MEMORY_BUS_WIDTH_64; // non-ECC only
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memcpy(dimm->serial, info->serial,
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memcpy(dimm->serial, info->serial,
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MIN(sizeof(dimm->serial), sizeof(info->serial)));
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MIN(sizeof(dimm->serial), sizeof(info->serial)));
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@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <device/dram/ddr2.h>
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#include <device/dram/ddr2.h>
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#include <device/dram/ddr3.h>
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#include <device/dram/spd.h>
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#include <device/dram/spd.h>
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#include <spd.h>
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#include <spd.h>
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#include <stddef.h>
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#include <stddef.h>
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@ -76,26 +77,26 @@ static void convert_ddr2_module_type_to_spd_info(enum spd_dimm_type_ddr2 module_
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}
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}
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}
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}
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static void convert_ddr3_module_type_to_spd_info(enum ddr3_module_type module_type,
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static void convert_ddr3_module_type_to_spd_info(enum spd_dimm_type_ddr3 module_type,
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struct spd_info *info)
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struct spd_info *info)
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{
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{
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switch (module_type) {
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switch (module_type) {
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case DDR3_SPD_RDIMM:
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case SPD_DDR3_DIMM_TYPE_RDIMM:
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case DDR3_SPD_MINI_RDIMM:
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case SPD_DDR3_DIMM_TYPE_MINI_RDIMM:
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info->form_factor = MEMORY_FORMFACTOR_RIMM;
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info->form_factor = MEMORY_FORMFACTOR_RIMM;
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info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
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info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
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break;
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break;
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case DDR3_SPD_UDIMM:
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case SPD_DDR3_DIMM_TYPE_UDIMM:
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case DDR3_SPD_MINI_UDIMM:
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case SPD_DDR3_DIMM_TYPE_MINI_UDIMM:
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info->form_factor = MEMORY_FORMFACTOR_DIMM;
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info->form_factor = MEMORY_FORMFACTOR_DIMM;
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info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
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info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
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break;
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break;
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case DDR3_SPD_MICRO_DIMM:
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case SPD_DDR3_DIMM_TYPE_MICRO_DIMM:
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info->form_factor = MEMORY_FORMFACTOR_DIMM;
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info->form_factor = MEMORY_FORMFACTOR_DIMM;
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info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
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info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
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break;
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break;
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case DDR3_SPD_SODIMM:
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case SPD_DDR3_DIMM_TYPE_SO_DIMM:
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case DDR3_SPD_72B_SO_UDIMM:
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case SPD_DDR3_DIMM_TYPE_72B_SO_UDIMM:
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info->form_factor = MEMORY_FORMFACTOR_SODIMM;
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info->form_factor = MEMORY_FORMFACTOR_SODIMM;
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info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
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info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
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break;
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break;
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@ -216,7 +217,7 @@ static uint8_t convert_ddrx_form_factor_to_module_type(smbios_memory_type memory
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return SPD_DDR2_DIMM_TYPE_RDIMM;
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return SPD_DDR2_DIMM_TYPE_RDIMM;
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case MEMORY_FORMFACTOR_SODIMM:
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case MEMORY_FORMFACTOR_SODIMM:
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module_type = (memory_type == MEMORY_TYPE_DDR2) ? SPD_DDR2_DIMM_TYPE_SO_DIMM :
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module_type = (memory_type == MEMORY_TYPE_DDR2) ? SPD_DDR2_DIMM_TYPE_SO_DIMM :
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DDR3_SPD_SODIMM;
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SPD_DDR3_DIMM_TYPE_SO_DIMM;
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return module_type;
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return module_type;
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default:
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default:
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return convert_default_form_factor_to_module_type();
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return convert_default_form_factor_to_module_type();
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@ -32,10 +32,7 @@
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#define SPD_DIMM_PART_LEN 18
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#define SPD_DIMM_PART_LEN 18
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/** @} */
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/** @} */
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/*
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/* Byte 3 [3:0]: DDR3 Module type information */
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* Module type (byte 3, bits 3:0) of SPD
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* This definition is specific to DDR3. DDR2 SPDs have a different structure.
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*/
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enum spd_dimm_type_ddr3 {
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enum spd_dimm_type_ddr3 {
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SPD_DDR3_DIMM_TYPE_UNDEFINED = 0x00,
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SPD_DDR3_DIMM_TYPE_UNDEFINED = 0x00,
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SPD_DDR3_DIMM_TYPE_RDIMM = 0x01,
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SPD_DDR3_DIMM_TYPE_RDIMM = 0x01,
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@ -201,23 +201,6 @@ enum spd_memory_type {
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#define SPD_ECC_8BIT (1<<3)
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#define SPD_ECC_8BIT (1<<3)
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#define SPD_ECC_8BIT_LP5_DDR5 (1<<4)
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#define SPD_ECC_8BIT_LP5_DDR5 (1<<4)
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/* Byte 3 [3:0]: DDR3 Module type information */
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enum ddr3_module_type {
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DDR3_SPD_RDIMM = 0x01,
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DDR3_SPD_UDIMM = 0x02,
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DDR3_SPD_SODIMM = 0x03,
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DDR3_SPD_MICRO_DIMM = 0x04,
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DDR3_SPD_MINI_RDIMM = 0x05,
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DDR3_SPD_MINI_UDIMM = 0x06,
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DDR3_SPD_MINI_CDIMM = 0x07,
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DDR3_SPD_72B_SO_UDIMM = 0x08,
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DDR3_SPD_72B_SO_RDIMM = 0x09,
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DDR3_SPD_72B_SO_CDIMM = 0x0a,
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DDR3_SPD_LRDIMM = 0x0b,
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DDR3_SPD_16B_SO_DIMM = 0x0c,
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DDR3_SPD_32B_SO_RDIMM = 0x0d,
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};
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/* Byte 3 [3:0]: DDR4 Module type information */
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/* Byte 3 [3:0]: DDR4 Module type information */
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enum ddr4_module_type {
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enum ddr4_module_type {
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DDR4_SPD_RDIMM = 0x01,
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DDR4_SPD_RDIMM = 0x01,
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@ -261,7 +261,7 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
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dimm->mod_id =
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dimm->mod_id =
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(pei_data->spd_data[index][SPD_DIMM_MOD_ID2] << 8) |
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(pei_data->spd_data[index][SPD_DIMM_MOD_ID2] << 8) |
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(pei_data->spd_data[index][SPD_DIMM_MOD_ID1] & 0xff);
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(pei_data->spd_data[index][SPD_DIMM_MOD_ID1] & 0xff);
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dimm->mod_type = DDR3_SPD_SODIMM;
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dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
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dimm->bus_width = MEMORY_BUS_WIDTH_64;
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dimm->bus_width = MEMORY_BUS_WIDTH_64;
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dimm_cnt++;
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dimm_cnt++;
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}
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}
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@ -433,7 +433,7 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
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dimm->mod_id = /* bytes 117/118 */
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dimm->mod_id = /* bytes 117/118 */
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(pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) |
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(pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) |
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(pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF);
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(pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF);
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dimm->mod_type = DDR3_SPD_SODIMM;
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dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
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dimm->bus_width = MEMORY_BUS_WIDTH_64;
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dimm->bus_width = MEMORY_BUS_WIDTH_64;
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dimm_cnt++;
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dimm_cnt++;
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}
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}
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@ -457,7 +457,7 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
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dimm->mod_id = /* bytes 117/118 */
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dimm->mod_id = /* bytes 117/118 */
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(pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) |
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(pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) |
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(pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF);
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(pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF);
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dimm->mod_type = DDR3_SPD_SODIMM;
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dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
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dimm->bus_width = MEMORY_BUS_WIDTH_64;
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dimm->bus_width = MEMORY_BUS_WIDTH_64;
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dimm_cnt++;
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dimm_cnt++;
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}
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}
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@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/dram/ddr2.h>
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#include <device/dram/ddr2.h>
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#include <device/dram/ddr3.h>
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#include <dimm_info_util.h>
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#include <dimm_info_util.h>
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#include <spd.h>
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#include <spd.h>
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#include <tests/test.h>
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#include <tests/test.h>
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@ -146,10 +147,12 @@ static void test_smbios_form_factor_to_spd_mod_type(void **state)
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},
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},
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{
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{
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.memory_type = MEMORY_TYPE_DDR3,
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.memory_type = MEMORY_TYPE_DDR3,
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.udimm_allowed = {DDR3_SPD_UDIMM, DDR3_SPD_MICRO_DIMM,
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.udimm_allowed = {SPD_DDR3_DIMM_TYPE_UDIMM,
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DDR3_SPD_MINI_UDIMM},
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SPD_DDR3_DIMM_TYPE_MICRO_DIMM,
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.rdimm_allowed = {DDR3_SPD_RDIMM, DDR3_SPD_MINI_RDIMM},
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SPD_DDR3_DIMM_TYPE_MINI_UDIMM},
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.expected_module_type = DDR3_SPD_SODIMM,
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.rdimm_allowed = {SPD_DDR3_DIMM_TYPE_RDIMM,
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SPD_DDR3_DIMM_TYPE_MINI_RDIMM},
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.expected_module_type = SPD_DDR3_DIMM_TYPE_SO_DIMM,
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},
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},
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{
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{
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.memory_type = MEMORY_TYPE_DDR4,
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.memory_type = MEMORY_TYPE_DDR4,
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