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spd.h: Move enum ddr3_module_type to ddr3.h 

Move specific enum ddr3_module_type to <device/dram/ddr3.h>.

Change-Id: I8fd7892dda26158a5bdd6cd4972c7859a252153e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71547
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes Haouas 2022-12-28 12:33:58 +01:00
parent af6cd3f0b4
commit f82e68c900
7 changed files with 22 additions and 60 deletions
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24
src/device/dram/ddr3.c
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@ -533,29 +533,7 @@ enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, const u16 selected
dimm->dimm_num = slot;
memcpy(dimm->module_part_number, info->part_number, 16);
dimm->mod_id = info->manufacturer_id;
switch (info->dimm_type) {
case SPD_DDR3_DIMM_TYPE_SO_DIMM:
dimm->mod_type = DDR3_SPD_SODIMM;
break;
case SPD_DDR3_DIMM_TYPE_72B_SO_CDIMM:
dimm->mod_type = DDR3_SPD_72B_SO_CDIMM;
break;
case SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM:
dimm->mod_type = DDR3_SPD_72B_SO_RDIMM;
break;
case SPD_DDR3_DIMM_TYPE_UDIMM:
dimm->mod_type = DDR3_SPD_UDIMM;
break;
case SPD_DDR3_DIMM_TYPE_RDIMM:
dimm->mod_type = DDR3_SPD_RDIMM;
break;
case SPD_DDR3_DIMM_TYPE_UNDEFINED:
default:
dimm->mod_type = SPD_UNDEFINED;
break;
}
dimm->mod_type = info->dimm_type;
dimm->bus_width = MEMORY_BUS_WIDTH_64; // non-ECC only
memcpy(dimm->serial, info->serial,
MIN(sizeof(dimm->serial), sizeof(info->serial)));

19
src/device/dram/spd.c
View File

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <device/dram/ddr2.h>
#include <device/dram/ddr3.h>
#include <device/dram/spd.h>
#include <spd.h>
#include <stddef.h>
@ -76,26 +77,26 @@ static void convert_ddr2_module_type_to_spd_info(enum spd_dimm_type_ddr2 module_
}
}
static void convert_ddr3_module_type_to_spd_info(enum ddr3_module_type module_type,
static void convert_ddr3_module_type_to_spd_info(enum spd_dimm_type_ddr3 module_type,
struct spd_info *info)
{
switch (module_type) {
case DDR3_SPD_RDIMM:
case DDR3_SPD_MINI_RDIMM:
case SPD_DDR3_DIMM_TYPE_RDIMM:
case SPD_DDR3_DIMM_TYPE_MINI_RDIMM:
info->form_factor = MEMORY_FORMFACTOR_RIMM;
info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
break;
case DDR3_SPD_UDIMM:
case DDR3_SPD_MINI_UDIMM:
case SPD_DDR3_DIMM_TYPE_UDIMM:
case SPD_DDR3_DIMM_TYPE_MINI_UDIMM:
info->form_factor = MEMORY_FORMFACTOR_DIMM;
info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
break;
case DDR3_SPD_MICRO_DIMM:
case SPD_DDR3_DIMM_TYPE_MICRO_DIMM:
info->form_factor = MEMORY_FORMFACTOR_DIMM;
info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
break;
case DDR3_SPD_SODIMM:
case DDR3_SPD_72B_SO_UDIMM:
case SPD_DDR3_DIMM_TYPE_SO_DIMM:
case SPD_DDR3_DIMM_TYPE_72B_SO_UDIMM:
info->form_factor = MEMORY_FORMFACTOR_SODIMM;
info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
break;
@ -216,7 +217,7 @@ static uint8_t convert_ddrx_form_factor_to_module_type(smbios_memory_type memory
return SPD_DDR2_DIMM_TYPE_RDIMM;
case MEMORY_FORMFACTOR_SODIMM:
module_type = (memory_type == MEMORY_TYPE_DDR2) ? SPD_DDR2_DIMM_TYPE_SO_DIMM :
DDR3_SPD_SODIMM;
SPD_DDR3_DIMM_TYPE_SO_DIMM;
return module_type;
default:
return convert_default_form_factor_to_module_type();

5
src/include/device/dram/ddr3.h
View File

@ -32,10 +32,7 @@
#define SPD_DIMM_PART_LEN 18
/** @} */
/*
* Module type (byte 3, bits 3:0) of SPD
* This definition is specific to DDR3. DDR2 SPDs have a different structure.
*/
/* Byte 3 [3:0]: DDR3 Module type information */
enum spd_dimm_type_ddr3 {
SPD_DDR3_DIMM_TYPE_UNDEFINED = 0x00,
SPD_DDR3_DIMM_TYPE_RDIMM = 0x01,

17
src/include/spd.h
View File

@ -201,23 +201,6 @@ enum spd_memory_type {
#define SPD_ECC_8BIT (1<<3)
#define SPD_ECC_8BIT_LP5_DDR5 (1<<4)
/* Byte 3 [3:0]: DDR3 Module type information */
enum ddr3_module_type {
DDR3_SPD_RDIMM = 0x01,
DDR3_SPD_UDIMM = 0x02,
DDR3_SPD_SODIMM = 0x03,
DDR3_SPD_MICRO_DIMM = 0x04,
DDR3_SPD_MINI_RDIMM = 0x05,
DDR3_SPD_MINI_UDIMM = 0x06,
DDR3_SPD_MINI_CDIMM = 0x07,
DDR3_SPD_72B_SO_UDIMM = 0x08,
DDR3_SPD_72B_SO_RDIMM = 0x09,
DDR3_SPD_72B_SO_CDIMM = 0x0a,
DDR3_SPD_LRDIMM = 0x0b,
DDR3_SPD_16B_SO_DIMM = 0x0c,
DDR3_SPD_32B_SO_RDIMM = 0x0d,
};
/* Byte 3 [3:0]: DDR4 Module type information */
enum ddr4_module_type {
DDR4_SPD_RDIMM = 0x01,

2
src/northbridge/intel/haswell/haswell_mrc/raminit.c
View File

@ -261,7 +261,7 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
dimm->mod_id =
(pei_data->spd_data[index][SPD_DIMM_MOD_ID2] << 8) |
(pei_data->spd_data[index][SPD_DIMM_MOD_ID1] & 0xff);
dimm->mod_type = DDR3_SPD_SODIMM;
dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
dimm->bus_width = MEMORY_BUS_WIDTH_64;
dimm_cnt++;
}

4
src/northbridge/intel/sandybridge/raminit_mrc.c
View File

@ -433,7 +433,7 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
dimm->mod_id = /* bytes 117/118 */
(pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) |
(pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF);
dimm->mod_type = DDR3_SPD_SODIMM;
dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
dimm->bus_width = MEMORY_BUS_WIDTH_64;
dimm_cnt++;
}
@ -457,7 +457,7 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
dimm->mod_id = /* bytes 117/118 */
(pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) |
(pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF);
dimm->mod_type = DDR3_SPD_SODIMM;
dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
dimm->bus_width = MEMORY_BUS_WIDTH_64;
dimm_cnt++;
}

11
tests/lib/dimm_info_util-test.c
View File

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/dram/ddr2.h>
#include <device/dram/ddr3.h>
#include <dimm_info_util.h>
#include <spd.h>
#include <tests/test.h>
@ -146,10 +147,12 @@ static void test_smbios_form_factor_to_spd_mod_type(void **state)
},
{
.memory_type = MEMORY_TYPE_DDR3,
.udimm_allowed = {DDR3_SPD_UDIMM, DDR3_SPD_MICRO_DIMM,
DDR3_SPD_MINI_UDIMM},
.rdimm_allowed = {DDR3_SPD_RDIMM, DDR3_SPD_MINI_RDIMM},
.expected_module_type = DDR3_SPD_SODIMM,
.udimm_allowed = {SPD_DDR3_DIMM_TYPE_UDIMM,
SPD_DDR3_DIMM_TYPE_MICRO_DIMM,
SPD_DDR3_DIMM_TYPE_MINI_UDIMM},
.rdimm_allowed = {SPD_DDR3_DIMM_TYPE_RDIMM,
SPD_DDR3_DIMM_TYPE_MINI_RDIMM},
.expected_module_type = SPD_DDR3_DIMM_TYPE_SO_DIMM,
},
{
.memory_type = MEMORY_TYPE_DDR4,