diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 03442970ad..899836c5f0 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -79,9 +79,11 @@
 /* Use either CBFS_CACHE (unified) or both (PRERAM|POSTRAM)_CBFS_CACHE */
 #define CBFS_CACHE(addr, size) REGION(cbfs_cache, addr, size, 4)
 
-/* TODO: This only works if you never access CBFS in romstage before RAM is up!
- * If you need to change that assumption, you have some work ahead of you... */
-#if defined(__PRE_RAM__) && !ENV_ROMSTAGE
+#if ENV_ROMSTAGE
+	#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
+	#define POSTRAM_CBFS_CACHE(addr, size) \
+		REGION(dram_cbfs_cache, addr, size, 4)
+#elif defined(__PRE_RAM__)
 	#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
 	#define POSTRAM_CBFS_CACHE(addr, size) \
 		REGION(unused_cbfs_cache, addr, size, 4)
diff --git a/src/include/symbols.h b/src/include/symbols.h
index 52fea48578..bf875aed57 100644
--- a/src/include/symbols.h
+++ b/src/include/symbols.h
@@ -41,6 +41,10 @@ extern u8 _stack[];
 extern u8 _estack[];
 #define _stack_size (_estack - _stack)
 
+extern u8 _dram_cbfs_cache[];
+extern u8 _edram_cbfs_cache[];
+#define _dram_cbfs_cache_size (_edram_cbfs_cache - _dram_cbfs_cache)
+
 extern u8 _cbfs_cache[];
 extern u8 _ecbfs_cache[];
 #define _cbfs_cache_size (_ecbfs_cache - _cbfs_cache)
diff --git a/src/lib/cbfs_spi.c b/src/lib/cbfs_spi.c
index 31a2e79e6c..82c3b834d3 100644
--- a/src/lib/cbfs_spi.c
+++ b/src/lib/cbfs_spi.c
@@ -22,6 +22,7 @@
 #include <boot_device.h>
 #include <spi_flash.h>
 #include <symbols.h>
+#include <cbmem.h>
 
 static struct spi_flash *spi_flash_info;
 
@@ -42,6 +43,12 @@ static const struct region_device_ops spi_ops = {
 static struct mmap_helper_region_device mdev =
 	MMAP_HELPER_REGION_INIT(&spi_ops, 0, CONFIG_ROM_SIZE);
 
+static void initialize_mdev(int unused)
+{
+	mmap_helper_device_init(&mdev, _dram_cbfs_cache, _dram_cbfs_cache_size);
+}
+ROMSTAGE_CBMEM_INIT_HOOK(initialize_mdev);
+
 void boot_device_init(void)
 {
 	int bus = CONFIG_BOOT_MEDIA_SPI_BUS;
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index 60fb5822cd..6ff2b77608 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -38,16 +38,7 @@ SECTIONS
 	QCA_SHARED_RAM(2A03F000, 4K)
 */
 	STACK(0x2A040000, 16K)
-#ifdef __PRE_RAM__
-       /*
-        * ipq8064 is different from most other ARM platforms: it loads the
-	* proprietary DRAM initialization code from CBFS (as opposed to compiling
-	* it in into rombase). As a result CBFS needs to be used before DRAM is
-	* availale, which means CBFS cache must be in SRAM, which in turn means
-	* that PRERAM_CBFS_CACHE description can not be used here.
-	*/
-	CBFS_CACHE(0x2A044000, 93K)
-#endif
+	PRERAM_CBFS_CACHE(0x2A044000, 93K)
 	TTB_SUBTABLES(0x2A05B800, 2K)
 	TTB(0x2A05C000, 16K)
 	SRAM_END(0x2A060000)
@@ -55,8 +46,6 @@ SECTIONS
 	DRAM_START(0x40000000)
 	RAMSTAGE(0x40640000, 128K)
 	SYMBOL(memlayout_cbmem_top, 0x59F80000)
-#ifndef __PRE_RAM__
-	CBFS_CACHE(0x59F80000, 384K)
-#endif
+	POSTRAM_CBFS_CACHE(0x59F80000, 384K)
 	DMA_COHERENT(0x5A000000, 2M)
 }