mb/google/hatch: Add mushu variant
Create initial overlays and build for mushu Signed-off-by: Bob Moragues <moragues@chromium.org> Change-Id: I81b5bf960ead0463159ac35f4f96e3ccc8c0364e Reviewed-on: https://review.coreboot.org/c/coreboot/+/37645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Bob Moragues
Patrick Georgi
parent
bd3037bfa7
commit
f82fa746bf
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@ -95,6 +95,7 @@ config MAINBOARD_PART_NUMBER
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default "Jinlon" if BOARD_GOOGLE_JINLON
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default "Kindred" if BOARD_GOOGLE_KINDRED
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default "Kohaku" if BOARD_GOOGLE_KOHAKU
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default "Mushu" if BOARD_GOOGLE_MUSHU
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default "Puff" if BOARD_GOOGLE_PUFF
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default "Stryke" if BOARD_GOOGLE_STRYKE
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@ -117,6 +118,7 @@ config VARIANT_DIR
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default "jinlon" if BOARD_GOOGLE_JINLON
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default "kindred" if BOARD_GOOGLE_KINDRED
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default "kohaku" if BOARD_GOOGLE_KOHAKU
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default "mushu" if BOARD_GOOGLE_MUSHU
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default "puff" if BOARD_GOOGLE_PUFF
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default "stryke" if BOARD_GOOGLE_STRYKE
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@ -38,6 +38,11 @@ config BOARD_GOOGLE_HELIOS
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select CHROMEOS_DSM_CALIB
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select DRIVERS_I2C_RT1011
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config BOARD_GOOGLE_MUSHU
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bool "-> Mushu"
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select BOARD_GOOGLE_BASEBOARD_HATCH
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select BOARD_ROMSIZE_KB_16384
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config BOARD_GOOGLE_PUFF
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bool "-> Puff"
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select BOARD_GOOGLE_BASEBOARD_HATCH
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@ -0,0 +1,23 @@
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## This file is part of the coreboot project.
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##
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## Copyright 2019 Google LLC
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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SPD_SOURCES = 4G_2400 # 0b000
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SPD_SOURCES += empty_ddr4 # 0b001
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SPD_SOURCES += 8G_2400 # 0b010
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SPD_SOURCES += 8G_2666 # 0b011
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SPD_SOURCES += 16G_2400 # 0b100
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SPD_SOURCES += 16G_2666 # 0b101
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ramstage-y += gpio.c
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bootblock-y += gpio.c
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@ -0,0 +1,69 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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static const struct pad_config gpio_table[] = {
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/* C13 : EC_PCH_INT_L */
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PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)};
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const struct pad_config *override_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(gpio_table);
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return gpio_table;
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}
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/*
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* GPIOs configured before ramstage
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* Note: the Hatch platform's romstage will configure
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* the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins
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* as inputs before it reads them, so they are not
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* needed in this table.
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*/
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static const struct pad_config early_gpio_table[] = {
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/* A12 : FPMCU_RST_ODL */
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PAD_CFG_GPO(GPP_A12, 0, DEEP),
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/* B15 : H1_SLAVE_SPI_CS_L */
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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/* B16 : H1_SLAVE_SPI_CLK */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
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/* B17 : H1_SLAVE_SPI_MISO_R */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C14 : BT_DISABLE_L */
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PAD_CFG_GPO(GPP_C14, 0, DEEP),
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/* PCH_WP_OD */
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PAD_CFG_GPI(GPP_C20, NONE, DEEP),
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/* C21 : H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
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/* C23 : WLAN_PE_RST# */
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PAD_CFG_GPO(GPP_C23, 1, DEEP),
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/* E1 : M2_SSD_PEDET */
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PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
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/* E5 : SATA_DEVSLP1 */
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PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
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/* F2 : MEM_CH_SEL */
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PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
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};
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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@ -0,0 +1,16 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/acpi/dptf.asl>
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef VARIANT_EC_H
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#define VARIANT_EC_H
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#include <baseboard/ec.h>
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#endif
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@ -0,0 +1,27 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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#include <baseboard/gpio.h>
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/* Memory configuration board straps */
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#define GPIO_MEM_CONFIG_0 GPP_F20
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#define GPIO_MEM_CONFIG_1 GPP_F21
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#define GPIO_MEM_CONFIG_2 GPP_F11
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#define GPIO_MEM_CONFIG_3 GPP_F22
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#endif
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@ -0,0 +1,181 @@
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chip soc/intel/cannonlake
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoPci,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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[PchSerialIoIndexSPI0] = PchSerialIoPci,
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[PchSerialIoIndexSPI1] = PchSerialIoPci,
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[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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# VR Slew rate setting
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register "AcousticNoiseMitigation" = "1"
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register "SlowSlewRateForIa" = "2"
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register "SlowSlewRateForGt" = "2"
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register "SlowSlewRateForSa" = "2"
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register "FastPkgCRampDisableIa" = "1"
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register "FastPkgCRampDisableGt" = "1"
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register "FastPkgCRampDisableSa" = "1"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| GSPI0 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| | before memory is up |
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#| GSPI1 | FP MCU |
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#| I2C0 | Touchpad |
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#| I2C1 | Touch screen |
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#| I2C4 | Audio |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.gspi[0] = {
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.speed_mhz = 1,
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.early_init = 1,
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},
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 50,
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.fall_time_ns = 15,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 60,
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.fall_time_ns = 25,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 150,
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.fall_time_ns = 150,
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},
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.i2c[4] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 120,
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.fall_time_ns = 120,
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},
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}"
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# GPIO for SD card detect
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register "sdcard_cd_gpio" = "vSD3_CD_B"
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device domain 0 on
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device pci 15.0 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)"
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register "wake" = "GPE0_DW0_21"
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device i2c 15 on end
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end
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end # I2C #0
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device pci 15.1 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0001""
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register "desc" = ""ELAN Touchscreen""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
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register "probed" = "1"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
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register "reset_delay_ms" = "100"
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register "reset_off_delay_ms" = "5"
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register "has_power_resource" = "1"
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register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
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register "stop_off_delay_ms" = "5"
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device i2c 49 on end
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end
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chip drivers/i2c/hid
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register "generic.hid" = ""GDIX0000""
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register "generic.desc" = ""Goodix Touchscreen""
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register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
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register "generic.probed" = "1"
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register "generic.reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
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register "generic.reset_delay_ms" = "120"
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register "generic.reset_off_delay_ms" = "3"
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register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
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register "generic.enable_delay_ms" = "12"
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register "generic.has_power_resource" = "1"
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register "hid_desc_reg_offset" = "0x01"
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device i2c 5d on end
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end
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chip drivers/generic/gpio_keys
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register "name" = ""PENH""
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register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)"
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register "key.wake" = "GPE0_DW0_08"
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register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
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register "key.dev_name" = ""EJCT""
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register "key.linux_code" = "SW_PEN_INSERTED"
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register "key.linux_input_type" = "EV_SW"
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register "key.label" = ""pen_eject""
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device generic 0 on end
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end
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end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 on
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chip drivers/i2c/sx9310
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register "desc" = ""SAR Proximity Sensor""
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register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)"
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register "speed" = "I2C_SPEED_FAST"
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register "uid" = "1"
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register "reg_prox_ctrl0" = "0x10"
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register "reg_prox_ctrl1" = "0x00"
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register "reg_prox_ctrl2" = "0x84"
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register "reg_prox_ctrl3" = "0x0e"
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register "reg_prox_ctrl4" = "0x07"
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register "reg_prox_ctrl5" = "0xc6"
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register "reg_prox_ctrl6" = "0x20"
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register "reg_prox_ctrl7" = "0x0d"
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register "reg_prox_ctrl8" = "0x8d"
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register "reg_prox_ctrl9" = "0x43"
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register "reg_prox_ctrl10" = "0x1f"
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register "reg_prox_ctrl11" = "0x00"
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register "reg_prox_ctrl12" = "0x00"
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register "reg_prox_ctrl13" = "0x00"
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register "reg_prox_ctrl14" = "0x00"
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register "reg_prox_ctrl15" = "0x00"
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register "reg_prox_ctrl16" = "0x00"
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register "reg_prox_ctrl17" = "0x00"
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register "reg_prox_ctrl18" = "0x00"
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register "reg_prox_ctrl19" = "0x00"
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register "reg_sar_ctrl0" = "0x50"
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register "reg_sar_ctrl1" = "0x8a"
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register "reg_sar_ctrl2" = "0x3c"
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device i2c 28 on end
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end
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end # I2C #3
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device pci 19.0 on
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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register "name" = ""RT58""
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register "desc" = ""Realtek RT5682""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
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register "property_count" = "1"
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# Set the jd_src to RT5668_JD1 for jack detection
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on end
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end
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end #I2C #4
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device pci 1e.3 on
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chip drivers/spi/acpi
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register "name" = ""CRFP""
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register "hid" = "ACPI_DT_NAMESPACE_HID"
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register "uid" = "1"
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register "compat_string" = ""google,cros-ec-spi""
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register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)"
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register "wake" = "GPE0_DW0_23"
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device spi 1 on end
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end # FPMCU
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end # GSPI #1
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end
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end
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