mb/google/hatch: Add mushu variant
Create initial overlays and build for mushu Signed-off-by: Bob Moragues <moragues@chromium.org> Change-Id: I81b5bf960ead0463159ac35f4f96e3ccc8c0364e Reviewed-on: https://review.coreboot.org/c/coreboot/+/37645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Bob Moragues
Patrick Georgi
parent
bd3037bfa7
commit
f82fa746bf
|
|
@ -95,6 +95,7 @@ config MAINBOARD_PART_NUMBER
|
||||||
default "Jinlon" if BOARD_GOOGLE_JINLON
|
default "Jinlon" if BOARD_GOOGLE_JINLON
|
||||||
default "Kindred" if BOARD_GOOGLE_KINDRED
|
default "Kindred" if BOARD_GOOGLE_KINDRED
|
||||||
default "Kohaku" if BOARD_GOOGLE_KOHAKU
|
default "Kohaku" if BOARD_GOOGLE_KOHAKU
|
||||||
|
default "Mushu" if BOARD_GOOGLE_MUSHU
|
||||||
default "Puff" if BOARD_GOOGLE_PUFF
|
default "Puff" if BOARD_GOOGLE_PUFF
|
||||||
default "Stryke" if BOARD_GOOGLE_STRYKE
|
default "Stryke" if BOARD_GOOGLE_STRYKE
|
||||||
|
|
||||||
|
|
@ -117,6 +118,7 @@ config VARIANT_DIR
|
||||||
default "jinlon" if BOARD_GOOGLE_JINLON
|
default "jinlon" if BOARD_GOOGLE_JINLON
|
||||||
default "kindred" if BOARD_GOOGLE_KINDRED
|
default "kindred" if BOARD_GOOGLE_KINDRED
|
||||||
default "kohaku" if BOARD_GOOGLE_KOHAKU
|
default "kohaku" if BOARD_GOOGLE_KOHAKU
|
||||||
|
default "mushu" if BOARD_GOOGLE_MUSHU
|
||||||
default "puff" if BOARD_GOOGLE_PUFF
|
default "puff" if BOARD_GOOGLE_PUFF
|
||||||
default "stryke" if BOARD_GOOGLE_STRYKE
|
default "stryke" if BOARD_GOOGLE_STRYKE
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -38,6 +38,11 @@ config BOARD_GOOGLE_HELIOS
|
||||||
select CHROMEOS_DSM_CALIB
|
select CHROMEOS_DSM_CALIB
|
||||||
select DRIVERS_I2C_RT1011
|
select DRIVERS_I2C_RT1011
|
||||||
|
|
||||||
|
config BOARD_GOOGLE_MUSHU
|
||||||
|
bool "-> Mushu"
|
||||||
|
select BOARD_GOOGLE_BASEBOARD_HATCH
|
||||||
|
select BOARD_ROMSIZE_KB_16384
|
||||||
|
|
||||||
config BOARD_GOOGLE_PUFF
|
config BOARD_GOOGLE_PUFF
|
||||||
bool "-> Puff"
|
bool "-> Puff"
|
||||||
select BOARD_GOOGLE_BASEBOARD_HATCH
|
select BOARD_GOOGLE_BASEBOARD_HATCH
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,23 @@
|
||||||
|
## This file is part of the coreboot project.
|
||||||
|
##
|
||||||
|
## Copyright 2019 Google LLC
|
||||||
|
##
|
||||||
|
## This program is free software; you can redistribute it and/or modify
|
||||||
|
## it under the terms of the GNU General Public License as published by
|
||||||
|
## the Free Software Foundation; version 2 of the License.
|
||||||
|
##
|
||||||
|
## This program is distributed in the hope that it will be useful,
|
||||||
|
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
## GNU General Public License for more details.
|
||||||
|
##
|
||||||
|
|
||||||
|
SPD_SOURCES = 4G_2400 # 0b000
|
||||||
|
SPD_SOURCES += empty_ddr4 # 0b001
|
||||||
|
SPD_SOURCES += 8G_2400 # 0b010
|
||||||
|
SPD_SOURCES += 8G_2666 # 0b011
|
||||||
|
SPD_SOURCES += 16G_2400 # 0b100
|
||||||
|
SPD_SOURCES += 16G_2666 # 0b101
|
||||||
|
|
||||||
|
ramstage-y += gpio.c
|
||||||
|
bootblock-y += gpio.c
|
||||||
|
|
@ -0,0 +1,69 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright 2019 Google LLC
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch/acpi.h>
|
||||||
|
#include <baseboard/gpio.h>
|
||||||
|
#include <baseboard/variants.h>
|
||||||
|
#include <commonlib/helpers.h>
|
||||||
|
|
||||||
|
static const struct pad_config gpio_table[] = {
|
||||||
|
/* C13 : EC_PCH_INT_L */
|
||||||
|
PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)};
|
||||||
|
|
||||||
|
const struct pad_config *override_gpio_table(size_t *num)
|
||||||
|
{
|
||||||
|
*num = ARRAY_SIZE(gpio_table);
|
||||||
|
return gpio_table;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GPIOs configured before ramstage
|
||||||
|
* Note: the Hatch platform's romstage will configure
|
||||||
|
* the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins
|
||||||
|
* as inputs before it reads them, so they are not
|
||||||
|
* needed in this table.
|
||||||
|
*/
|
||||||
|
static const struct pad_config early_gpio_table[] = {
|
||||||
|
/* A12 : FPMCU_RST_ODL */
|
||||||
|
PAD_CFG_GPO(GPP_A12, 0, DEEP),
|
||||||
|
/* B15 : H1_SLAVE_SPI_CS_L */
|
||||||
|
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
|
||||||
|
/* B16 : H1_SLAVE_SPI_CLK */
|
||||||
|
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
|
||||||
|
/* B17 : H1_SLAVE_SPI_MISO_R */
|
||||||
|
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
|
||||||
|
/* B18 : H1_SLAVE_SPI_MOSI_R */
|
||||||
|
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
|
||||||
|
/* C14 : BT_DISABLE_L */
|
||||||
|
PAD_CFG_GPO(GPP_C14, 0, DEEP),
|
||||||
|
/* PCH_WP_OD */
|
||||||
|
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
|
||||||
|
/* C21 : H1_PCH_INT_ODL */
|
||||||
|
PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
|
||||||
|
/* C23 : WLAN_PE_RST# */
|
||||||
|
PAD_CFG_GPO(GPP_C23, 1, DEEP),
|
||||||
|
/* E1 : M2_SSD_PEDET */
|
||||||
|
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
|
||||||
|
/* E5 : SATA_DEVSLP1 */
|
||||||
|
PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
|
||||||
|
/* F2 : MEM_CH_SEL */
|
||||||
|
PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
|
||||||
|
};
|
||||||
|
|
||||||
|
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||||
|
{
|
||||||
|
*num = ARRAY_SIZE(early_gpio_table);
|
||||||
|
return early_gpio_table;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,16 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2019 Intel Corporation.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <baseboard/acpi/dptf.asl>
|
||||||
|
|
@ -0,0 +1,21 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright 2019 Google LLC
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef VARIANT_EC_H
|
||||||
|
#define VARIANT_EC_H
|
||||||
|
|
||||||
|
#include <baseboard/ec.h>
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,27 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright 2019 Google LLC
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef VARIANT_GPIO_H
|
||||||
|
#define VARIANT_GPIO_H
|
||||||
|
|
||||||
|
#include <baseboard/gpio.h>
|
||||||
|
|
||||||
|
/* Memory configuration board straps */
|
||||||
|
#define GPIO_MEM_CONFIG_0 GPP_F20
|
||||||
|
#define GPIO_MEM_CONFIG_1 GPP_F21
|
||||||
|
#define GPIO_MEM_CONFIG_2 GPP_F11
|
||||||
|
#define GPIO_MEM_CONFIG_3 GPP_F22
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,181 @@
|
||||||
|
chip soc/intel/cannonlake
|
||||||
|
|
||||||
|
register "SerialIoDevMode" = "{
|
||||||
|
[PchSerialIoIndexI2C0] = PchSerialIoPci,
|
||||||
|
[PchSerialIoIndexI2C1] = PchSerialIoPci,
|
||||||
|
[PchSerialIoIndexI2C2] = PchSerialIoPci,
|
||||||
|
[PchSerialIoIndexI2C3] = PchSerialIoPci,
|
||||||
|
[PchSerialIoIndexI2C4] = PchSerialIoPci,
|
||||||
|
[PchSerialIoIndexI2C5] = PchSerialIoPci,
|
||||||
|
[PchSerialIoIndexSPI0] = PchSerialIoPci,
|
||||||
|
[PchSerialIoIndexSPI1] = PchSerialIoPci,
|
||||||
|
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
|
||||||
|
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
|
||||||
|
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
|
||||||
|
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
|
||||||
|
}"
|
||||||
|
|
||||||
|
# VR Slew rate setting
|
||||||
|
register "AcousticNoiseMitigation" = "1"
|
||||||
|
register "SlowSlewRateForIa" = "2"
|
||||||
|
register "SlowSlewRateForGt" = "2"
|
||||||
|
register "SlowSlewRateForSa" = "2"
|
||||||
|
register "FastPkgCRampDisableIa" = "1"
|
||||||
|
register "FastPkgCRampDisableGt" = "1"
|
||||||
|
register "FastPkgCRampDisableSa" = "1"
|
||||||
|
|
||||||
|
# Intel Common SoC Config
|
||||||
|
#+-------------------+---------------------------+
|
||||||
|
#| Field | Value |
|
||||||
|
#+-------------------+---------------------------+
|
||||||
|
#| GSPI0 | cr50 TPM. Early init is |
|
||||||
|
#| | required to set up a BAR |
|
||||||
|
#| | for TPM communication |
|
||||||
|
#| | before memory is up |
|
||||||
|
#| GSPI1 | FP MCU |
|
||||||
|
#| I2C0 | Touchpad |
|
||||||
|
#| I2C1 | Touch screen |
|
||||||
|
#| I2C4 | Audio |
|
||||||
|
#+-------------------+---------------------------+
|
||||||
|
register "common_soc_config" = "{
|
||||||
|
.gspi[0] = {
|
||||||
|
.speed_mhz = 1,
|
||||||
|
.early_init = 1,
|
||||||
|
},
|
||||||
|
.i2c[0] = {
|
||||||
|
.speed = I2C_SPEED_FAST,
|
||||||
|
.rise_time_ns = 50,
|
||||||
|
.fall_time_ns = 15,
|
||||||
|
},
|
||||||
|
.i2c[1] = {
|
||||||
|
.speed = I2C_SPEED_FAST,
|
||||||
|
.rise_time_ns = 60,
|
||||||
|
.fall_time_ns = 25,
|
||||||
|
},
|
||||||
|
.i2c[3] = {
|
||||||
|
.speed = I2C_SPEED_FAST,
|
||||||
|
.rise_time_ns = 150,
|
||||||
|
.fall_time_ns = 150,
|
||||||
|
},
|
||||||
|
.i2c[4] = {
|
||||||
|
.speed = I2C_SPEED_FAST,
|
||||||
|
.rise_time_ns = 120,
|
||||||
|
.fall_time_ns = 120,
|
||||||
|
},
|
||||||
|
}"
|
||||||
|
|
||||||
|
# GPIO for SD card detect
|
||||||
|
register "sdcard_cd_gpio" = "vSD3_CD_B"
|
||||||
|
|
||||||
|
device domain 0 on
|
||||||
|
device pci 15.0 on
|
||||||
|
chip drivers/i2c/generic
|
||||||
|
register "hid" = ""ELAN0000""
|
||||||
|
register "desc" = ""ELAN Touchpad""
|
||||||
|
register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)"
|
||||||
|
register "wake" = "GPE0_DW0_21"
|
||||||
|
device i2c 15 on end
|
||||||
|
end
|
||||||
|
end # I2C #0
|
||||||
|
device pci 15.1 on
|
||||||
|
chip drivers/i2c/generic
|
||||||
|
register "hid" = ""ELAN0001""
|
||||||
|
register "desc" = ""ELAN Touchscreen""
|
||||||
|
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
|
||||||
|
register "probed" = "1"
|
||||||
|
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
|
||||||
|
register "reset_delay_ms" = "100"
|
||||||
|
register "reset_off_delay_ms" = "5"
|
||||||
|
register "has_power_resource" = "1"
|
||||||
|
register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
|
||||||
|
register "stop_off_delay_ms" = "5"
|
||||||
|
device i2c 49 on end
|
||||||
|
end
|
||||||
|
chip drivers/i2c/hid
|
||||||
|
register "generic.hid" = ""GDIX0000""
|
||||||
|
register "generic.desc" = ""Goodix Touchscreen""
|
||||||
|
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
|
||||||
|
register "generic.probed" = "1"
|
||||||
|
register "generic.reset_gpio" =
|
||||||
|
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
|
||||||
|
register "generic.reset_delay_ms" = "120"
|
||||||
|
register "generic.reset_off_delay_ms" = "3"
|
||||||
|
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
|
||||||
|
register "generic.enable_delay_ms" = "12"
|
||||||
|
register "generic.has_power_resource" = "1"
|
||||||
|
register "hid_desc_reg_offset" = "0x01"
|
||||||
|
device i2c 5d on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/gpio_keys
|
||||||
|
register "name" = ""PENH""
|
||||||
|
register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)"
|
||||||
|
register "key.wake" = "GPE0_DW0_08"
|
||||||
|
register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
|
||||||
|
register "key.dev_name" = ""EJCT""
|
||||||
|
register "key.linux_code" = "SW_PEN_INSERTED"
|
||||||
|
register "key.linux_input_type" = "EV_SW"
|
||||||
|
register "key.label" = ""pen_eject""
|
||||||
|
device generic 0 on end
|
||||||
|
end
|
||||||
|
end # I2C #1
|
||||||
|
device pci 15.2 off end # I2C #2
|
||||||
|
device pci 15.3 on
|
||||||
|
chip drivers/i2c/sx9310
|
||||||
|
register "desc" = ""SAR Proximity Sensor""
|
||||||
|
register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)"
|
||||||
|
register "speed" = "I2C_SPEED_FAST"
|
||||||
|
register "uid" = "1"
|
||||||
|
register "reg_prox_ctrl0" = "0x10"
|
||||||
|
register "reg_prox_ctrl1" = "0x00"
|
||||||
|
register "reg_prox_ctrl2" = "0x84"
|
||||||
|
register "reg_prox_ctrl3" = "0x0e"
|
||||||
|
register "reg_prox_ctrl4" = "0x07"
|
||||||
|
register "reg_prox_ctrl5" = "0xc6"
|
||||||
|
register "reg_prox_ctrl6" = "0x20"
|
||||||
|
register "reg_prox_ctrl7" = "0x0d"
|
||||||
|
register "reg_prox_ctrl8" = "0x8d"
|
||||||
|
register "reg_prox_ctrl9" = "0x43"
|
||||||
|
register "reg_prox_ctrl10" = "0x1f"
|
||||||
|
register "reg_prox_ctrl11" = "0x00"
|
||||||
|
register "reg_prox_ctrl12" = "0x00"
|
||||||
|
register "reg_prox_ctrl13" = "0x00"
|
||||||
|
register "reg_prox_ctrl14" = "0x00"
|
||||||
|
register "reg_prox_ctrl15" = "0x00"
|
||||||
|
register "reg_prox_ctrl16" = "0x00"
|
||||||
|
register "reg_prox_ctrl17" = "0x00"
|
||||||
|
register "reg_prox_ctrl18" = "0x00"
|
||||||
|
register "reg_prox_ctrl19" = "0x00"
|
||||||
|
register "reg_sar_ctrl0" = "0x50"
|
||||||
|
register "reg_sar_ctrl1" = "0x8a"
|
||||||
|
register "reg_sar_ctrl2" = "0x3c"
|
||||||
|
device i2c 28 on end
|
||||||
|
end
|
||||||
|
end # I2C #3
|
||||||
|
device pci 19.0 on
|
||||||
|
chip drivers/i2c/generic
|
||||||
|
register "hid" = ""10EC5682""
|
||||||
|
register "name" = ""RT58""
|
||||||
|
register "desc" = ""Realtek RT5682""
|
||||||
|
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
|
||||||
|
register "property_count" = "1"
|
||||||
|
# Set the jd_src to RT5668_JD1 for jack detection
|
||||||
|
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
|
||||||
|
register "property_list[0].name" = ""realtek,jd-src""
|
||||||
|
register "property_list[0].integer" = "1"
|
||||||
|
device i2c 1a on end
|
||||||
|
end
|
||||||
|
end #I2C #4
|
||||||
|
device pci 1e.3 on
|
||||||
|
chip drivers/spi/acpi
|
||||||
|
register "name" = ""CRFP""
|
||||||
|
register "hid" = "ACPI_DT_NAMESPACE_HID"
|
||||||
|
register "uid" = "1"
|
||||||
|
register "compat_string" = ""google,cros-ec-spi""
|
||||||
|
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)"
|
||||||
|
register "wake" = "GPE0_DW0_23"
|
||||||
|
device spi 1 on end
|
||||||
|
end # FPMCU
|
||||||
|
end # GSPI #1
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
Loading…
Reference in New Issue