nehalem/raminit: remove read_mchbar functions
Change-Id: I7935cc166aa39f4053f45eef925d92ce50fd98ba Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Felix Held
parent
22ca8cb415
commit
f83d80bfe8
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@ -96,20 +96,6 @@ struct ram_training {
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#include <lib.h> /* Prototypes */
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static inline u32 read_mchbar32(u32 addr)
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{
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return MCHBAR32(addr);
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}
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static inline u16 read_mchbar16(u32 addr)
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{
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return MCHBAR16(addr);
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}
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static inline u8 read_mchbar8(u32 addr)
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{
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return MCHBAR8(addr);
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}
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static void clflush(u32 addr)
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{
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@ -3676,8 +3662,7 @@ static void dmi_setup(void)
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gav(read8(DEFAULT_DMIBAR + 0x254));
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write8(DEFAULT_DMIBAR + 0x254, 0x1);
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write16(DEFAULT_DMIBAR + 0x1b8, 0x18f2);
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read_mchbar16(0x48);
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MCHBAR16(0x48) = 0x2;
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MCHBAR16_AND_OR(0x48, 0, 0x2);
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write32(DEFAULT_DMIBAR + 0xd68, read32(DEFAULT_DMIBAR + 0xd68) | 0x08000000);
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@ -3711,8 +3696,7 @@ void chipset_init(const int s3resume)
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MCHBAR16(0x1170) = 0xa880;
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MCHBAR8(0x11c1) = 0x1;
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MCHBAR16(0x1170) = 0xb880;
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read_mchbar8(0x1210);
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MCHBAR8(0x1210) = 0x84;
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MCHBAR8_AND_OR(0x1210, 0, 0x84);
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if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) {
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/* 0 for 32MB */
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@ -3731,8 +3715,7 @@ void chipset_init(const int s3resume)
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pci_read_config8(NORTHBRIDGE, 0x8); // = 0x18
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MCHBAR16_OR(0x2c30, 0x200);
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MCHBAR16(0x2c32) = 0x434;
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read_mchbar32(0x2c44);
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MCHBAR32(0x2c44) = 0x1053687;
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MCHBAR32_AND_OR(0x2c44, 0, 0x1053687);
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pci_read_config8(GMA, 0x62); // = 0x2
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pci_write_config8(GMA, 0x62, 0x2);
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read8(DEFAULT_RCBA + 0x2318);
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@ -3741,8 +3724,7 @@ void chipset_init(const int s3resume)
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write8(DEFAULT_RCBA + 0x2320, 0xfc);
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}
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read_mchbar32(0x30);
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MCHBAR32(0x30) = 0x40;
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MCHBAR32_AND_OR(0x30, 0, 0x40);
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pci_write_config16(NORTHBRIDGE, D0F0_GGC, ggc);
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gav(read32(DEFAULT_RCBA + 0x3428));
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@ -3758,6 +3740,11 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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u16 deven;
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int cbmem_wasnot_inited;
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/* only used for dummy reads */
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volatile u8 tmp8;
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volatile u16 tmp16;
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volatile u32 tmp32;
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x2ca8 = MCHBAR8(0x2ca8);
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deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN);
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@ -4060,24 +4047,22 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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set_2dxx_series(&info, s3resume);
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if (!(deven & 8)) {
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read_mchbar32(0x2cb0);
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MCHBAR32(0x2cb0) = 0x40;
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MCHBAR32_AND_OR(0x2cb0, 0, 0x40);
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}
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udelay(1000);
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if (deven & 8) {
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MCHBAR32_OR(0xff8, 0x1800);
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read_mchbar32(0x2cb0);
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MCHBAR32(0x2cb0) = 0x00;
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MCHBAR32_AND(0x2cb0, 0x00);
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pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c);
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pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c);
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pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4e);
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read_mchbar8(0x1150);
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read_mchbar8(0x1151);
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read_mchbar8(0x1022);
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read_mchbar8(0x16d0);
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tmp8 = MCHBAR8(0x1150);
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tmp8 = MCHBAR8(0x1151);
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tmp8 = MCHBAR8(0x1022);
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tmp8 = MCHBAR8(0x16d0);
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MCHBAR32(0x1300) = 0x60606060;
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MCHBAR32(0x1304) = 0x60606060;
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MCHBAR32(0x1308) = 0x78797a7b;
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@ -4128,13 +4113,11 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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MCHBAR16(0x11c0) = 0xc40b;
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MCHBAR16(0x11c2) = 0x303;
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MCHBAR16(0x11c4) = 0x301;
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read_mchbar32(0x1190);
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MCHBAR32(0x1190) = 0x8900080a;
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MCHBAR32_AND_OR(0x1190, 0, 0x8900080a);
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MCHBAR32(0x11b8) = 0x70c3000;
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MCHBAR8(0x11ec) = 0xa;
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MCHBAR16(0x1100) = 0x800;
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read_mchbar32(0x11bc);
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MCHBAR32(0x11bc) = 0x1e84800;
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MCHBAR32_AND_OR(0x11bc, 0, 0x1e84800);
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MCHBAR16(0x11ca) = 0xfa;
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MCHBAR32(0x11e4) = 0x4e20;
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MCHBAR8(0x11bc) = 0xf;
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@ -4168,10 +4151,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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if ((deven & 8) && x2ca8 == 0) {
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MCHBAR16(0x1214) = 0x320;
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MCHBAR32(0x1600) = 0x40000000;
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read_mchbar32(0x11f4);
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MCHBAR32(0x11f4) = 0x10000000;
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read_mchbar16(0x1230);
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MCHBAR16(0x1230) = 0x8000;
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MCHBAR32_AND_OR(0x11f4, 0, 0x10000000);
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MCHBAR16_AND_OR(0x1230, 0, 0x8000);
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MCHBAR32(0x1400) = 0x13040020;
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MCHBAR32(0x1404) = 0xe090120;
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MCHBAR32(0x1408) = 0x5120220;
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@ -4268,12 +4249,11 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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MCHBAR16(0x1220) = 0x1388;
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}
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read_mchbar32(0x2c80); // !!!!
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MCHBAR32(0x2c80) = 0x1053688;
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read_mchbar32(0x1c04); // !!!!
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MCHBAR32_AND_OR(0x2c80, 0, 0x1053688); // !!!!
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tmp32 = MCHBAR32(0x1c04); // !!!!
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MCHBAR32(0x1804) = 0x406080;
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read_mchbar8(0x2ca8);
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tmp8 = MCHBAR8(0x2ca8);
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if (x2ca8 == 0) {
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MCHBAR8_AND(0x2ca8, ~3);
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@ -4283,12 +4263,11 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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}
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MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8);
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read_mchbar32(0x2c80); // !!!!
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MCHBAR32(0x2c80) = 0x53688;
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MCHBAR32_AND_OR(0x2c80, 0, 0x53688); // !!!!
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pci_write_config32(PCI_DEV (0xff, 0, 0), 0x60, 0x20220);
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read_mchbar16(0x2c20); // !!!!
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read_mchbar16(0x2c10); // !!!!
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read_mchbar16(0x2c00); // !!!!
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tmp16 = MCHBAR16(0x2c20); // !!!!
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tmp16 = MCHBAR16(0x2c10); // !!!!
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tmp16 = MCHBAR16(0x2c00); // !!!!
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MCHBAR16(0x2c00) = 0x8c0;
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udelay(1000);
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write_1d0(0, 0x33d, 0, 0);
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@ -4301,10 +4280,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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MCHBAR16(0x616) = 0x26a;
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MCHBAR32(0x134) = 0x856000;
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MCHBAR32(0x160) = 0x5ffffff;
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read_mchbar32(0x114); // !!!!
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MCHBAR32(0x114) = 0xc2024440;
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read_mchbar32(0x118); // !!!!
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MCHBAR32(0x118) = 0x4;
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MCHBAR32_AND_OR(0x114, 0, 0xc2024440); // !!!!
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MCHBAR32_AND_OR(0x118, 0, 0x4); // !!!!
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for (channel = 0; channel < NUM_CHANNELS; channel++)
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MCHBAR32(0x260 + (channel << 10)) = 0x30809ff |
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((info.populated_ranks_mask[channel] & 3) << 20);
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@ -4394,12 +4371,10 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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write_1d0(info.cached_training->reg_10b, 0x10b, 6, 1);
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}
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read_mchbar32(0x1f4); // !!!!
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MCHBAR32(0x1f4) = 0x20000;
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MCHBAR32_AND_OR(0x1f4, 0, 0x20000); // !!!!
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MCHBAR32(0x1f0) = 0x1d000200;
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read_mchbar8(0x1f0); // !!!!
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MCHBAR8(0x1f0) = 0x1;
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read_mchbar8(0x1f0); // !!!!
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MCHBAR8_AND_OR(0x1f0, 0, 0x1); // !!!!
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tmp8 = MCHBAR8(0x1f0); // !!!!
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program_board_delay(&info);
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@ -4427,10 +4402,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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write_1d0(0, 0xae, 6, 1);
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read_1d0(0x300, 4); // = 0x48088080 // !!!!
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write_1d0(0, 0x300, 6, 1);
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read_mchbar16(0x356); // !!!!
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MCHBAR16(0x356) = 0x1040;
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read_mchbar16(0x756); // !!!!
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MCHBAR16(0x756) = 0x1040;
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MCHBAR16_AND_OR(0x356, 0, 0x1040); // !!!!
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MCHBAR16_AND_OR(0x756, 0, 0x1040); // !!!!
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MCHBAR32_AND(0x140, ~0x07000000);
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MCHBAR32_AND(0x138, ~0x07000000);
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MCHBAR32(0x130) = 0x31111301;
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@ -4460,7 +4433,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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info.populated_ranks[channel][0][0] ? 9 : 1);
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rmw_1d0(0x116, 0xe, 1, 4, 1); // = 0x4040432 // !!!!
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read_mchbar32(0x144); // !!!!
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tmp32 = MCHBAR32(0x144); // !!!!
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write_1d0(2, 0xae, 6, 1);
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write_1d0(2, 0x300, 6, 1);
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write_1d0(2, 0x121, 3, 1);
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@ -4537,10 +4510,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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MCHBAR8(0x12c) = 0x9f;
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read_mchbar8(0x271); // 2 // !!!!
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MCHBAR8(0x271) = 0xe;
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read_mchbar8(0x671); // !!!!
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MCHBAR8(0x671) = 0xe;
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MCHBAR8_AND_OR(0x271, 0, 0xe); // 2 // !!!!
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MCHBAR8_AND_OR(0x671, 0, 0xe); // !!!!
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if (!s3resume) {
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for (channel = 0; channel < NUM_CHANNELS; channel++) {
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@ -4551,8 +4522,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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(info.populated_ranks[channel][0][1] << 5);
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MCHBAR32(0x29c + (channel << 10)) = 0x77a;
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}
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read_mchbar32(0x2c0); /// !!!
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MCHBAR32(0x2c0) = 0x6009cc00;
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MCHBAR32_AND_OR(0x2c0, 0, 0x6009cc00); // !!!!
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{
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u8 a, b;
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@ -4601,8 +4571,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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(info.populated_ranks[channel][0][1] << 5);
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MCHBAR32(0x29c + (channel << 10)) = 0x77a;
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}
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read_mchbar32(0x2c0); /// !!!
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MCHBAR32(0x2c0) = 0x6009cc00;
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MCHBAR32_AND_OR(0x2c0, 0, 0x6009cc00); // !!!!
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}
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MCHBAR32_AND(0xfa4, ~0x01000002);
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@ -4714,7 +4683,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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reg1c = read32p(DEFAULT_EPBAR | 0x01c); // = 0x8001 // OK
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pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
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write32p(DEFAULT_EPBAR | 0x01c, reg1c); // OK
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read_mchbar8(0xe08); // = 0x0
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tmp8 = MCHBAR8(0xe08); // = 0x0
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pci_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126
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MCHBAR8_OR(0x1210, 2);
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MCHBAR32(0x1200) = 0x8800440;
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